SLUA560D June   2011  – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1

 

  1.   Trademarks
  2. 1 Design Specifications
  3. 2 Functional Schematic
  4. 3 Power Budget
  5. 4 Transformer Calculations (T1)
  6. 5 QA, QB, QC, QD FET Selection
  7. 6 Selecting LS
  8. 7 Output Inductor Selection (LOUT)
  9. 8 Output Capacitance (COUT)
  10. 9 Select FETs QE and QF
  11. 10Input Capacitance (CIN)
  12. 11Setting Up the Current Sense (CS) Network (CT, RS, RRE, DA)
  13. 12Voltage Loop and Slope Compensation
  14. 13Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)
  15. 14Turning SR FETs-off Under Light Load Conditions
  16. 15600 W FSFB Detailed Schematic and Test Data
  17. 16References
  18. 17Revision History

15 600 W FSFB Detailed Schematic and Test Data

GUID-1020D959-F3A7-490F-B509-F1D66DC9A4B9-low.gif Figure 15-1 Daughter Board Schematic
Note:

Black triangles designate not populated.

Figure 15-2 Power Stage Schematic
Note:

It is recommended to use an RCD clamp to protect the output synchronous FETs from over voltage due to switch node ringing. This RCD clamp is formed by diodes D4, D6 and resistor R6, R8 and R9 and capacitor C1.

Figure 15-3 600-W Phase Shifted Full Bridge Efficiency

Full bridge gate drives and primary switch nodes (QBd and QDd) at VIN = 390 V, IOUT = 5 A.

Figure 15-4 Q4g Q4d, VIN = 390 V, IOUT = 5 A
Figure 15-5 Q3g Q3d, VIN = 390 V, IOUT = 5 A

Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 10 A

Figure 15-6 Q4g Q4d, VIN = 390 V, IOUT = 10 A
Figure 15-7 Q3g Q3d, VIN = 390 V, IOUT = 10 A
Note:

Switch node QBd/Q4d is valley switching and node QDd/Q3d has achieved ZVS. It is not uncommon for switch node QDd/Q3d to obtain ZVS before QBd/Q4d. This is because during the QDd/Q3d switch node voltage transition, the reflected output current provides immediate energy for the LC tanking at the switch node. Where at the QBd/Q4d switch node transition the primary has been shorted out by the high side or low side FETs in the H bridge. This transition is dependent on the energy stored in LS and LLK to provide energy for the LC tanking at switch node QBd/Q4d making it take longer to achieve ZVS.

Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 25 A

Figure 15-8 Q4g Q4d, VIN = 390 V, IOUT = 25 A
Figure 15-9 Q3g Q3d, VIN = 390 V, IOUT = 25 A
Note:

When the converter is running at 25 A both switch nodes are operating into zero voltage switching (ZVS). It is also worth mentioning that there is no evidence of the gate miller plateau during gate driver switching. This makes sense because the voltage across the drain and source of FETs QA through QD has already transition before the gate drives have transitioned.

Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 50 A

Figure 15-10 Q4g Q4d, VIN = 390 V, IOUT = 25 A
Figure 15-11 Q3g Q3d, VIN = 390 V, IOUT = 25 A
Note:

ZVS was maintained from 50% to 100% output power.