SLVAEG1A August   2019  – May 2021 TLV62568 , TLV62568A , TPS62840

 

  1.   Trademarks
  2. 1Introduction
  3. 2Highlighted Products
  4. 3Buck Converter Architectures
  5. 4Testing Setup
  6. 5Testing Results
  7. 6Results Summary
  8. 7Further Reading
  9. 8Revision History

2 Highlighted Products

Architecture A is implemented with the buck converter TLV62568 and the LDO TPS7A05.

TLV62568 is a high-efficiency, cost-effective buck converter utilizing an adaptive off-time with peak current control topology. The device operates at typically 1.5-MHz frequency PWM at moderate to heavy load currents. Based on the VIN/V­OUT ratio, a simple circuit sets the required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and load current. The current of the high-side switch is sensed for peak current control, and implements a switch current limit to prevent the device from drawing excessive current from a battery, or input voltage rail. Once the high-side switch current limit is reached, the high-side switch is turned off, and the low-side switch is turned on to ramp down the inductor current with an adaptive off-time.

TPS7A05 is an ultra-small, low quiescent current LDO that can source 200 mA with excellent transient performance. This device has an output range of 0.8 V to 3.3 V with a typical 1% accuracy. This LDO offers foldback current limit, shutdown, and thermal protection.

Architecture B is implemented with the FPWM version of the same buck converter from Architecture A, TLV62568A. As such, the control topology and functionality are essentially the same,but with the difference of TLV62568A staying in PWM mode at light loads while the TLV62568 goes into pulse frequency modulation (PFM) operation at light loads.

Architecture C is implemented with buck converter TPS62841, which has an ultra-low nominal IQ of 60 nA, high light-load efficiency, and utilizes DCS-Control™. DCS–Control is a high-performance control scheme that combines the advantages of hysteretic and voltage mode controls. This combination allows for excellent AC load regulation and transient response, low output ripple voltage, and a seamless transition between PFM and PWM modes with minimum output voltage ripple. It includes an AC loop that senses the output voltage and directly feeds this information into a fast comparator stage. An additional voltage feedback loop is used to achieve accurate DC load regulation, and an internally compensated regulation network achieves fast and stable operation with small, external components and low ESR capacitors. In PFM, or Power-Save Mode, the switching frequency varies linearly with the load current.