SLVAF45 August 2021 TPS51397A , TPS566231 , TPS566235 , TPS566238 , TPS568230
Figure 5-1 is the design flow chart for D-CAP2/D-CAP3 converter with Cff. All the inductance and capacitance used in choosing Cff are effective value considering degrading.
Here TPS568230 is used as an example to illustrate the design method for a 5V Vo application. The condition of example is Vin=12 V, Vo=5 V, Ioutmax=8 A, fsw=600kHz.
First select voltage divider resistors R1(Rtop)=220 kΩ and R2(Rbottom)=30 kΩ to achieve 5 V output with 0.6 V reference voltage. Then, same as the analysis mentioned in section 2, the range of inductance can be got as 1.52 uH-3.04 uH, according to the principle to limit inductor current ripple as 20%-40% of Ioutmax. And we can select 744311220 inductor and its effective inductance with 8 A current is about 1.8 uH.
About 180uF output capacitance are used to meet output ripple requirement. Here the 885012108012 MLCC are used. With about 52.5% degrading at 5 V bias for the 47 uF capacitance, the effective capacitance of each MLCC is about 22.35 uF. Capacitance of 8 parallel MLCCs are 178.8 uF.
Then the method is used to select Cff. As Acp=29.3 and ωRI=270 k for TPS568230, we can get Cff>44 pF according to Equation 14 and Equation 15. Here we can choose 120 pF Cff.