SNLA473 November   2024 DP83867CS , DP83867E , DP83867IS , DP83869HM , DP83TC811S-Q1 , DP83TC812S-Q1 , DP83TC813S-Q1 , DP83TC814S-Q1 , DP83TC817S-Q1 , DP83TC818S-Q1 , DP83TG720S-Q1 , DP83TG721S-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Troubleshooting the MAC Interface - SGMII
    1. 1.1 Verify Bootstrap Configurations
      1. 1.1.1 SGMII Bootstrap Configuration for DP83TG720S-Q1
    2. 1.2 Read and Check Register Values
    3. 1.3 Auto-Negotiation
    4. 1.4 Throughput and Loopback Testing
      1. 1.4.1 Bidirectional Throughput Testing
      2. 1.4.2 RX and TX Throughput Testing
      3. 1.4.3 RX and TX Throughput Testing with Fixed Number of Packets
      4. 1.4.4 Loopback Testing
        1. 1.4.4.1 MII Loopback
        2. 1.4.4.2 Reverse Loopback
    5. 1.5 Check the Clock Signal
    6. 1.6 Measure the SGMII Eye
      1. 1.6.1 SGMII Eye Mask Requirements
    7. 1.7 SGMII Layout
  5. 2Summary
  6. 3References

1.7 SGMII Layout

Another cause of packet loss, errors, and link down can be length mismatches and discontinuities in SGMII traces. Traces needs to have minimal bends and RX traces needs to be length matched to RX traces and TX traces needs to be length matched to TX traces to make sure of proper transmission of data and successful link up every time the system is powered on.

Additionally, make sure that 100nf AC coupling capacitors have been placed close to the transmitter pins. There needs to also be differential impedance of 100Ω present across the traces and the traces need to be less than 6 inches.

A full layout checkout can be found in the schematic checklist found Design Tools and Simulation section of each product page.