SPRAC94D September   2018  – March 2022 AFE030 , AFE031 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1 FSK Overview
  3. 2 Hardware Overview
    1. 2.1 Block Diagram
    2. 2.2 Hardware Setup
  4. 3 Interfacing With the AFE03x
    1. 3.1 Configuring the AFE031
  5. 4 Transmit Path
    1. 4.1 FSK Example Specifications
    2. 4.2 PWM Mode
      1. 4.2.1 Software Implementation
      2. 4.2.2 Testing Results
      3. 4.2.3 HRPWM vs. EPWM
    3. 4.3 DAC Mode
      1. 4.3.1 Software Implementation
      2. 4.3.2 Testing Results
      3. 4.3.3 OFDM Ability
    4. 4.4 Porting TX to LAUNCHXL-F280049C
      1. 4.4.1 PWM Mode Specific Porting
      2. 4.4.2 DAC Mode Specific Porting
  6. 5 Receive Path
    1. 5.1 Receive Path Overview
    2. 5.2 Receiver Software Implementation
      1. 5.2.1 Initial Setup and Parameters
      2. 5.2.2 Interrupt Service Routines
      3. 5.2.3 Run Time Operation
      4. 5.2.4 Testing Results
      5. 5.2.5 System Utilization
      6. 5.2.6 Device Dependency and Porting
    3. 5.3 Tuning and Calibration
      1. 5.3.1 Setting the AFE03X's PGAs
      2. 5.3.2 Automatic Gain Control (AGC)
      3. 5.3.3 Setting the Bit Detection Threshold
      4. 5.3.4 FSK Correlation Detector Library
    4. 5.4 Porting RX to LAUNCHXL-F280049C
  7. 6 Interfacing With a Power Line
    1. 6.1 Line Coupling
    2. 6.2 Coupling to an AC Line
      1. 6.2.1 Low Voltage Capacitor
      2. 6.2.2 The Ratio of the Transformer
      3. 6.2.3 HV Capacitor
      4. 6.2.4 HV Side Inductor
    3. 6.3 Coupling to DC Line
    4. 6.4 Protection Circuit
      1. 6.4.1 Metal Oxide Varistors
      2. 6.4.2 Transient Voltage Suppressors
      3. 6.4.3 Current Steering Diodes
    5. 6.5 Determining PA Power Supply Requirements
  8. 7 Summary
  9. 8 References
  10. 9 Schematics
    1. 9.1 Schematics (PWM Mode)
    2. 9.2 Schematics (DAC Mode)
  11. 10Revision History

5.2.5 System Utilization

The resources consumed by the C2000 MCU when being used as an FSK receiver are listed in Table 5-5.

Table 5-5 C2000 Resources Utilized
Resource Name Type Purpose Usage/Restrictions
ADCINA Module/IO ADC input for sampling input signal Restricted to ADC inputs that are available an accessible
EPwm1 Module Triggers the interrupt for the signal sampling routine Can be configured a number of ways to meet desired ISR frequency
EPwm2 Module Triggers the interrupt for running the bit decision routine Can be configured a number of ways to meet desired ISR frequency
SPI Module/IO For accessing the AFE03x’s registers during initialization Only needed for initialization for the RX solution
CPU Timer 2 Module Can be used to create a timeout when no information has been received for a certain amount of time ISR may have lower priority than other set ISRs

The number of CPU cycles consumed by each fsk_corr_detect library function are listed in Table 5-6.

Table 5-6 Library Function CPU Cycles
Function Name Description CPU Cycles Type
FSK_CORR_DETECTOR_INIT Initializes variables used by the FSK library, based off the frequency parameters the user sets within a fsk_corr_detector structure 60 Initialization
FSK_CORR_DETECTOR_
RUN		 Performs necessary calculations on the sampled ADC values to demodulate the input signal 59 Run Time

FSK_CORR_DETECTOR_
OverSampl_RUN

 Performs the logic to decipher if a bit has been received 134 Run Time
Packetize Takes a received message data buffer and builds usable code words and packets 1381 Run Time

The run-time CPU utilization of the software solution, when being used in its default state and receiving information specified in Table 4-1, can be calculated using the information in Table 5-7.

Table 5-7 Software ISR/Function Usage
ISR/Function Average Cycles Frequency of Execution
ADC Sampling ISR 74 300 kHz
Bit-decision ISR 175 Approximately 586 Hz
Packetization Function 1381 Approximately 1 Hz

CPU Utilization Equation:

CPU Utilization = ((74*FS + 175*3*Fbit + 1381*FPacketization) / FCPU)*100%

CPU Utilization at F28379D's 200 MHz Clocking Frequency:

CPU Utilization =((74*300kHz + 175*586Hz + 1381*1Hz) / 200MHz)*100% = 11.15%