SPRAC94D September   2018  – March 2022 AFE030 , AFE031 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. FSK Overview
  3. Hardware Overview
    1. 2.1 Block Diagram
    2. 2.2 Hardware Setup
  4. Interfacing With the AFE03x
    1. 3.1 Configuring the AFE031
  5. Transmit Path
    1. 4.1 FSK Example Specifications
    2. 4.2 PWM Mode
      1. 4.2.1 Software Implementation
      2. 4.2.2 Testing Results
      3. 4.2.3 HRPWM vs. EPWM
    3. 4.3 DAC Mode
      1. 4.3.1 Software Implementation
      2. 4.3.2 Testing Results
      3. 4.3.3 OFDM Ability
    4. 4.4 Porting TX to LAUNCHXL-F280049C
      1. 4.4.1 PWM Mode Specific Porting
      2. 4.4.2 DAC Mode Specific Porting
  6. Receive Path
    1. 5.1 Receive Path Overview
    2. 5.2 Receiver Software Implementation
      1. 5.2.1 Initial Setup and Parameters
      2. 5.2.2 Interrupt Service Routines
      3. 5.2.3 Run Time Operation
      4. 5.2.4 Testing Results
      5. 5.2.5 System Utilization
      6. 5.2.6 Device Dependency and Porting
    3. 5.3 Tuning and Calibration
      1. 5.3.1 Setting the AFE03X's PGAs
      2. 5.3.2 Automatic Gain Control (AGC)
      3. 5.3.3 Setting the Bit Detection Threshold
      4. 5.3.4 FSK Correlation Detector Library
    4. 5.4 Porting RX to LAUNCHXL-F280049C
  7. Interfacing With a Power Line
    1. 6.1 Line Coupling
    2. 6.2 Coupling to an AC Line
      1. 6.2.1 Low Voltage Capacitor
      2. 6.2.2 The Ratio of the Transformer
      3. 6.2.3 HV Capacitor
      4. 6.2.4 HV Side Inductor
    3. 6.3 Coupling to DC Line
    4. 6.4 Protection Circuit
      1. 6.4.1 Metal Oxide Varistors
      2. 6.4.2 Transient Voltage Suppressors
      3. 6.4.3 Current Steering Diodes
    5. 6.5 Determining PA Power Supply Requirements
  8. Summary
  9. References
  10. Schematics
    1. 9.1 Schematics (PWM Mode)
    2. 9.2 Schematics (DAC Mode)
  11. 10Revision History

Initial Setup and Parameters

The FSK signals being received follow a set of communication parameters that must be designed around within software.

GUID-54F9F16F-2C7D-4916-B9BD-79BC06296509-low.jpgFigure 5-4 Received FSK Signal

The communication parameters of interest are illustrated in Figure 5-4. The labeled parameters represent the following:

  • Tbit : Bit Period
  • Fbit : Bit Frequency
  • Fmark : Mark Frequency
  • Fspace : Space Frequency
  • TS : Sampling Period
  • FS : Sampling Frequency

For the example program the communication parameters being followed by default are stated in Table 4-1. Create a FSK_CORR_DETECTOR structure, declared in fsk_corr_detector.h, to hold the parameters necessary for accurate receiving.

   volatile FSK_CORR_DETECTOR FSK_struct1; // FSK structure

The example software and fsk_corr_detect library are designed to detect a set of user specified frequencies, one mark frequency and one space frequency. These frequencies will have to be within the frequency band ranges of the AFE031's CENELEC A or CENELEC B,C,D configurations. The example program utilizes a mark frequency of 131.25 kHz and a space frequency of 143.75 kHz and is meant to be used with the CENELEC B,C,D configuration. Set the mark_freq and space_freq members of the FSK_CORR_DETECTOR structure with these frequencies.

   FSK_struct1.mark_freq = 131250;    // Mark Frequency Detected
   FSK_struct1.space_freq = 143750;   // Space Frequency Detected

The C2000's ADC is used to sample the FSK input signal. The sampling frequency, FS, must follow the Nyquist theorem; the input signal must be sampled at a rate of at least 2x the highest signal frequency trying to be detected. That is, if the highest signal frequency to be detected is 100 kHz, FS must be at least 200 kHz. In the example program the highest frequency being detected is a 143.75 kHz space frequency and the sampling rate is set to 300 kHz, which is more than the required rate. Set the isr_freq member of the FSK_CORR_DETECTOR structure to the acceptable FS.

   FSK_struct1.isr_freq = 300000;     // ADC Sampling frequency

A bit decision algorithm is intended to be run at three times the bit frequency. For example, if each bit period is 1 ms long, the bit frequency is 1 kHz making the desired bit decision frequency 3 kHz. The example program is detecting bits with a period of 5.12 ms making the bit frequency 195.3125 Hz and the desired bit decision frequency 585.9375 Hz. The bit decision frequency in software should be as close as possible to the desired frequency to prevent bit boundary issues. Set the bit_freq member of the FSK_CORR_DETECTOR structure with this bit decision frequency.

   FSK_struct1.bit_freq = 586; // Bit decision frequency, 3x bit frequency
            

In summary, the frequency parameters set for the example program are shown in Table 5-4.

Table 5-4 Software Frequency Parameters
ParameterFrequency
Detected Mark Frequency131.25 kHz
Detected Space Frequency143.75 kHz
Input Signal Sampling Frequency300 kHz
Bit Decision Algorithm Frequency586 Hz (rounded up)

Set the detection_threshold member of the FSK_CORR_DETECTOR structure. This value plays a role in tuning the bit detection senstivity.

   #define FSK_BIT_DETECTION_THRESHOLD 0.1 // Bit detection threshold value
   FSK_struct1.detection_threshold = FSK_BIT_DETECTION_THRESHOLD; // Set threshold
            

Complete the fsk_corr_detect library's initialization based on the member values inputted by calling the corresponding init function.

   FSK_CORR_DETECTOR_INIT(&FSK_struct1); // Initialize FSK structure
            

Additionally, the format of received information is taken into account by setting the following parameters within software.

  • The number of bits that make up a word, #define within fsk_packetization.h:
    • #define NUMBER_OF_BITS_PER_WORD 11
  • The number of words that make up a packet, #define within fsk_packetization.h:
    • #define NUMBER_OF_WORDS 3
  • The number of total bits within a packet, #define within fsk_corr_detector.h:
    • #define RX_MESSAGE_SIZE 33