SPRAC94D September   2018  – March 2022 AFE030 , AFE031 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1 FSK Overview
  3. 2 Hardware Overview
    1. 2.1 Block Diagram
    2. 2.2 Hardware Setup
  4. 3 Interfacing With the AFE03x
    1. 3.1 Configuring the AFE031
  5. 4 Transmit Path
    1. 4.1 FSK Example Specifications
    2. 4.2 PWM Mode
      1. 4.2.1 Software Implementation
      2. 4.2.2 Testing Results
      3. 4.2.3 HRPWM vs. EPWM
    3. 4.3 DAC Mode
      1. 4.3.1 Software Implementation
      2. 4.3.2 Testing Results
      3. 4.3.3 OFDM Ability
    4. 4.4 Porting TX to LAUNCHXL-F280049C
      1. 4.4.1 PWM Mode Specific Porting
      2. 4.4.2 DAC Mode Specific Porting
  6. 5 Receive Path
    1. 5.1 Receive Path Overview
    2. 5.2 Receiver Software Implementation
      1. 5.2.1 Initial Setup and Parameters
      2. 5.2.2 Interrupt Service Routines
      3. 5.2.3 Run Time Operation
      4. 5.2.4 Testing Results
      5. 5.2.5 System Utilization
      6. 5.2.6 Device Dependency and Porting
    3. 5.3 Tuning and Calibration
      1. 5.3.1 Setting the AFE03X's PGAs
      2. 5.3.2 Automatic Gain Control (AGC)
      3. 5.3.3 Setting the Bit Detection Threshold
      4. 5.3.4 FSK Correlation Detector Library
    4. 5.4 Porting RX to LAUNCHXL-F280049C
  7. 6 Interfacing With a Power Line
    1. 6.1 Line Coupling
    2. 6.2 Coupling to an AC Line
      1. 6.2.1 Low Voltage Capacitor
      2. 6.2.2 The Ratio of the Transformer
      3. 6.2.3 HV Capacitor
      4. 6.2.4 HV Side Inductor
    3. 6.3 Coupling to DC Line
    4. 6.4 Protection Circuit
      1. 6.4.1 Metal Oxide Varistors
      2. 6.4.2 Transient Voltage Suppressors
      3. 6.4.3 Current Steering Diodes
    5. 6.5 Determining PA Power Supply Requirements
  8. 7 Summary
  9. 8 References
  10. 9 Schematics
    1. 9.1 Schematics (PWM Mode)
    2. 9.2 Schematics (DAC Mode)
  11. 10Revision History

4.2.1 Software Implementation

Example program referenced: boostxl_afe031_f28379d_pwmmode

To enable PWM mode in software, the following flow needs to be completed:

  • Enable PWM transmit mode
    • To enable the PWM transmit mode, set the TX and PA bits in the enable register to 1, and set the DAC bit to 0.
    • Software example function: HAL_afe031_txPWMEnable();
  • Disable the DAC transmit mode

Two PWM sources are used to create the two PWM signals: one PWM source is used to set the frequency of the two outputted signals and the other controls the bit rate for the sent data. In the software example, PWM2 is used to control the bit rate and generate an interrupt to determine the frequency that needs to be outputted.

In the software example, the PWM2 interrupt handles all of the FSK protocol requirements. The implemented protocol is a repeatable pattern, which allows the software to be based on a cycle count. One cycle count is the time period for one bit. In this implementation, 33 bits (11 bits per word, three words) are sent. During each cycle, it checks the value of the next bit and the PWM frequency changes to either the mark or space frequencies. After 33 cycles, the system stops sending PWM signals and enters the quiet mode. After 209 cycles, the cycle count is reset and the software starts sending the packet again.With the FSK transmission being handled by the PWM2 interrupt, the CPU's main function is free to be used for other applications. By default the software example will transmit a packet_1 referenced in Table 4-1, but this can be changed to a packet_0 by setting the packet_to_send variable to a zero.