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  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Resources
      1. 1.1.1 TINA-TI SPICE-Based Analog Simulation Program
      2. 1.1.2 PSPICE for TI Design and Simulation Tool
      3. 1.1.3 Application Report: ADC Input Circuit Evaluation for C2000 MCUs
      4. 1.1.4 TI Precision Labs - SAR ADC Input Driver Design Series
      5. 1.1.5 Analog Engineer's Calculator
      6. 1.1.6 TI Precision Labs - Op Amps: Stability Series
        1. 1.1.6.1 Related Application Reports
      7. 1.1.7 TINA-TI ADC Input Models
  4. 2Charge-Sharing Concept
    1. 2.1 Traditional High-Speed ADC Driving Circuits
    2. 2.2 Increased Cs in High-Speed ADC Driving Circuits
    3. 2.3 Very Large Cs in ADC Driving Circuits
    4. 2.4 Charge-Sharing Operation
    5. 2.5 Sample Rate and Source Impedance vs. Tracking Error
    6. 2.6 Analytical Solution to Tracking Error
    7. 2.7 Charge-Sharing in Multiplexed ADCs
    8. 2.8 Charge-Sharing Circuit Advantages
    9. 2.9 Charge-Sharing Circuit Disadvantages
  5. 3Charge Sharing Design Flow
    1. 3.1 Gather Required Information
    2. 3.2 Size Cs
    3. 3.3 Verify Sample Rate, Source Impedance, and Bandwidth
    4. 3.4 Simulate Circuit Settling Performance
    5. 3.5 Input Design Worksheet
  6. 4Charge-Sharing Circuit Simulation Methods
    1. 4.1 Simulation Components
      1. 4.1.1 Vin
      2. 4.1.2 Voa , Voa_SS, and Verror
      3. 4.1.3 Rs, Cs, and Vcont
      4. 4.1.4 Ch, Ron, and Cp
      5. 4.1.5 S+H Switch, Discharge Switch, tacq, and tdis
    2. 4.2 Configure the Simulation Parameters
    3. 4.3 Simulating Op-amp Steady-State Voltage
    4. 4.4 Measure the Settling Error
    5. 4.5 Sweeping Source Resistance
  7. 5Example Circuit Designs
    1. 5.1 Example 1: Determining Maximum Sample Rate
      1. 5.1.1 Example 1: Analysis
      2. 5.1.2 Example 1: Simulation
      3. 5.1.3 Example 1: Worksheet
    2. 5.2 Example 2: Adding an Op-amp
      1. 5.2.1 Example 2: Analysis
      2. 5.2.2 Example 2: Simulation
      3. 5.2.3 Example 2: Worksheet
    3. 5.3 Example 3: Reduced Settling Target
      1. 5.3.1 Example 3: Analysis
      2. 5.3.2 Example 3: Simulation
      3. 5.3.3 Example 3: Worksheet
    4. 5.4 Example 4: Voltage Divider
      1. 5.4.1 Example 4: Analysis
      2. 5.4.2 Example 4: Simulation
      3. 5.4.3 Example 4: Worksheet
  8. 6Summary
  9.   A Appendix: ADC Input Settling Motivation
    1.     A.1 Mechanism of ADC Input Settling
    2.     A.2 Symptoms of Inadequate Settling
      1.      A.2.1 Distortion
      2.      A.2.2 Memory Cross-Talk
      3.      A.2.3 Accuracy
      4.      A.2.4 C2000 ADC Architecture
  10.   References
  11.   Revision History

5.3.3 Example 3: Worksheet

Table 5-3 Example 3: ADC Charge Sharing Design Worksheet
SymbolDescriptionValueComments
NTarget settling resolution (bits)7
(to get 8-bit settling)		Usually the same as the resolution of the ADC.
Lower resolution can be targeted to relax the input design requirements
VfsFull scale voltage range3.0 VIn external reference mode, this is the voltage supplied to the VREFHI pin (usually 3.0 V or 2.5 V)
In internal reference mode, this is the effective input range based on the selected reference mode (usually 3.3 V or 2.5 V)
VerrmaxMaximum error target11.7 mV Vfs / 2N+1
Can be further divided into two components: charge-sharing error and tracking error, each Verrmax / 2
tshS+H time 80 nsAs long as Cs is sized appropriately for charge-sharing, the minimum value from the ADC data manual can be used.
ChADC S+H capacitance12.5 pFProvided in the data manual table "Input Model Parameters"
CpADC pin parasitic capacitance0 pF (assumed negligible)Provided in the data manual table "Per-Channel Parasitic Capacitance"
Cs Source capacitance6.8 nFAt least (2N+2 ⋅ CH) - Cp
Rs Source resistanceN/A

Output resistance of source driving ADC. Can also be intentionally selected.

fsSample Rate96 kspsSample rate on channel of interest. Usually a requirement from the application.
BWs Source signal required bandwidth. lowSource signal required bandwidth.
RsmaxMax allowable source resistance2188ΩIf fs is known, calculate as 1 / (0.7⋅fs⋅Cs),
then ensure that Rs < Rsmax . If the condition is not met, additional design iteration is needed.
fsmaxMax allowable sampling frequencyN/AIf Rs is known, calculate as 1 / (0.7⋅Rs⋅Cs),
then ensure that fs < fsmax.
If the condition is not met, additional design iteration is needed.
BWRsCsFilter bandwidth from Cs and Rs 10.7 kHz1 / (2π⋅Cs⋅Rs )
Ensure that BWRsCs > BWs , otherwise additional design iteration is needed.
Voa_ssSteady state op-amp output voltage3 VIf no op-amp is used, set Voa_ss = Vfs. Otherwise, this can be generated from DC nodal analysis of the Voa node. Copy to Voa_ss before proceeding with other simulations.
BWOPAADC driver op-amp minimum bandwidth N/AIf an op-amp is needed, bandwidth should be at least 4 times BWRsCs
Op-ampSelected Op-amp part numberN/ARecord selected op-amp here (if needed).
VerrActual settling error from simulation10.9 mVEnsure Verr < Verrmax
Otherwise, additional design iteration is needed