The primary configuration that needs to be done for charge-sharing simulations is to set the sample rate. This is controlled by settings of the piecewise linear voltage sources t_acq and t_dis.

Sample t_acq timing configurations for a 100 ns acquisition window and 100kHz sampling are shown in Figure 4-3. The first four lines configure the S+H window to occur from 0 to 102 ns with 1 ns rise and fall times. The last line (which is of primary interest) configures how often the waveform repeats. This effectively sets the sample rate, so 10000 ns (10 µs) is equivalent to 100 kHz sampling.

Figure 4-3 Example Timings for t_acq (Piecewise Linear)

Sample t_dis timing configurations for a 100 ns discharge period and 100 kHz sampling are shown in Figure 4-4. The first five lines specify a 100 ns discharge period with 10ns rise and fall times starting at 9.87 µs. The last line configures how often the waveform repeats. This effectively sets the sample rate, so 10000 ns (10 µs) is equivalent to 100 kHz sampling. Ensure that the last line of the tdis and t_acq timings always exactly match! It is not necessary for this discharge period to occur exactly at the end of the triggering period, so it is acceptable to change the sampling rate by only changing the last line. For example, changing the final line of both t_dis and t_acq to 20000 ns will change the sample rate to 50 kHz. Do, however, ensure that the discharge period does not overlap with the S+H period in t_acq as this will result in the input being shorted to ground instead of charging C_H.

Figure 4-4 Example Timings for t_dis (Piecewise Linear)

Note that the timings are configured to emulate conversions triggered at 100 kHz frequency. This slower sample rate on a specific channel is typical of a charge-sharing input design (instead of back-to-back continuous conversions at the max ADC sample rate). The triggering rate can be modified to match the actual application ePWM trigger rate by modifying the period of the t_acq and t_dis timing sources. Do, however, ensure that the trigger rate is slower than the total S+H plus acquisition time for the ADC conversion. The ADC conversion time can be found in the device-specific data manual table "ADC Timings".