Due to the high effective source impedance of the voltage divider along with the design not using an op-amp buffer to drive the ADC channel, voltage V2 will experience significant S+H settling error. Since the system uses a multiplexed sampling scheme where ADCA samples voltage V1 before V2 each time a trigger is received, this settling error will manifest as memory cross-talk from V1 to V2 as show in Figure 3-4. This means that when V1 is lower than V2, the sample results from V2 will be pulled lower and when V1 is higher than V2, the results of V2 will be pulled higher. Furthermore, the magnitude of this error is expected to be about 130 mV if V1 and V2 are at opposite extremes of the ADC's input range (as shown by the simulation in Figure 3-3).

Generally, since V1 and V2 independent signals being sampled by the system, the memory cross-talk error induced in V2 will vary unpredictably. This will likely result in poor system performance and instability. Ideally, the signal conditioning circuits driving V2 would be redesigned to ensure good settling performance, but this is not always feasible due to additional system constraints or working with a fixed existing system. Section 4 and Section 5 present methods for transforming the memory cross-talk error into a form that is more systematic and predictable.