When configuring the ADC to use VREFLO samples to mitigate memory cross-talk, several decisions need to be made. With respect to the selected S+H duration, two values need to be selected: the S+H duration for the channel sampling VREFLO and the S+H duration for the channel sampling the signal of interest. The channel sampling VREFLO can use the minimum S+H window allowed by the ADC, but some care needs to be taken to select the S+H for the channel of interest. The more settling error the selected S+H produces, the more gain error needs to be compensated out of the system. In general, the magnitude of this gain error should be kept to a reasonable level because a larger value will be more sensitive to component tolerances. Furthermore, the attenuation of the input signal caused by the gain error could cause less of the ADC input range to be used by the application, reducing dynamic range of the signal. For these reasons, it is recommended that the S+H be selected to keep the gain error less than about 5% of the ADC full-scale range (even though calibration should be able to remove most of this error).

With a method to select the S+H duration determined, the user has all the information needed to design a system using the VREFLO pre-sampling method. They should follow the following steps:

• Add additional SOCs to the ADC sampling sequence and configure those SOCs to sample the internal connection to VREFLO using the minimum S+H window duration allowable (or another convenient and valid S+H duration)
• Simulate the settling error with different S+H durations to determine a S+H duration that gives a settling error less than about 5% of the ADC full-scale range
• Determine the compensation coefficients for each channel benefiting from the VREFLO sampling method through either (1) simulation of the settling error or (2) direct measurement of the settling error. Once the settling error is determined, the coefficient, C_i, is given by the equation below, where V_in was the input voltage applied to the system or simulation.

• The use should add compensation code to their CPU ISR or CLA task to modify the raw ADC result using the following formula. V_i is the raw ADC result affected by the VREFLO sampling, V_i' is the compensated result, and C_i is the compensation coefficient determined in the previous step.