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  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Mechanism of ADC Input Settling
    2. 1.2 Symptoms of Inadequate Settling
      1. 1.2.1 Distortion
      2. 1.2.2 Memory Cross-Talk
      3. 1.2.3 Accuracy
      4. 1.2.4 C2000 ADC Architecture
    3. 1.3 Resources
      1. 1.3.1 TINA-TI SPICE-Based Analog Simulation Program
      2. 1.3.2 PSPICE for TI Design and Simulation Tool
      3. 1.3.3 TI Precision Labs - SAR ADC Input Driver Design Series
      4. 1.3.4 Analog Engineer's Calculator
      5. 1.3.5 Related Application Reports
      6. 1.3.6 PSpice for TI ADC Input Models
  4. 2Input Settling Design Steps
    1. 2.1 Select the ADC
    2. 2.2 Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
      1. 2.2.1 Select Type
      2. 2.2.2 Resolution
      3. 2.2.3 Csh
      4. 2.2.4 Full-Scale Range
      5. 2.2.5 Acquisition Time
      6. 2.2.6 Outputs
      7. 2.2.7 Math Behind the Calculator
    3. 2.3 Select an Op-Amp
    4. 2.4 Verify the Op-Amp Model
    5. 2.5 Build the ADC Input Model
      1. 2.5.1 Vin
      2. 2.5.2 Voa, Voa_SS, and Verror
      3. 2.5.3 Rs, Cs, and Vcont
      4. 2.5.4 Ch, Ron, and Cp
      5. 2.5.5 S+H Switch, Discharge Switch, tacq, and tdis
    6. 2.6 Refine RC Filter Values Via Simulation
    7. 2.7 Perform Final Simulations
    8. 2.8 Input Design Worksheet
  5. 3Example Circuit Design
    1. 3.1  Select the ADC
    2. 3.2  Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
    3. 3.3  Verify the Op-Amp Model
    4. 3.4  Build the ADC Input Model
    5. 3.5  Bias Point Analysis to Determine Voa_ss
    6. 3.6  Transient Analysis to Determine Voa_ss
    7. 3.7  Perform Initial Transient Analysis
    8. 3.8  Iterative Approach to Refine RC Filter Values
    9. 3.9  Perform Final Transient Analysis
    10. 3.10 Perform Final Transient Analysis
    11. 3.11 Further Refinement
    12. 3.12 Further Simulations
    13. 3.13 Completed Worksheet
  6. 4Working With Existing Circuits or Additional Constraints
    1. 4.1 Existing Circuits
      1. 4.1.1 Brief Overview of Charge Sharing
      2. 4.1.2 Charge Sharing Example
      3. 4.1.3 Additional Resources for Charge Sharing
    2. 4.2 Pre-Selected Op-Amp
      1. 4.2.1 Pre-Selected Op-Amp Example
    3. 4.3 Pre-Selected Rs and Cs Values
      1. 4.3.1 Analytical Solution for ADC Acquisition Time
      2. 4.3.2 Example Analytical Solution for ADC Acquisition Time
  7. 5Summary
  8. 6References

2.8 Input Design Worksheet

Table 3-3 lists the required inputs needed to evaluate an ADC input driving circuit and provides a place to summarize the outputs. Completing this worksheet for each unique circuit in your real-time control application is recommended to ensure good settling performance. For some circuits, it may be desirable to use the alternate design methodology presented in the application report Charge-Sharing Driving Circuits for C2000 ADCs (using PSPICE-FOR-TI simulation tool). That report also provides a worksheet that can be evaluated using the alternate design methodology.

Table 2-2 ADC Input Settling Design Worksheet
Symbol Description Value Comments
Vfs Full scale voltage range In external reference mode, this is the voltage supplied to the VREFHI pin (usually 3.0V or 2.5 V)
In internal reference mode, this is the effective input range based on the selected reference mode (usually 3.3 V or 2.5 V)
N Target settling resolution (bits) Usually the same as the resolution of the ADC
Lower resolution can be targeted to relax the input design requirements
Verrmax Maximum error target Vfs / 2N+1
Obtain using Analog Engineer's Calculator: ADC SAR Drive
tsh S+H time Enter target S+H time if known
Longer S+H times will result in less stringent BW requirements for the driving op-amp.
Can be solved for given a pre-determined op-amp selection or a pre-determined RS and CS
Ron ADC switch resistance Provided in the Input Model Parameters table in the device-specific data manual
TI Precision Labs training refers to this as "Rsh"
Ch ADC S+H capacitance Provided in the Input Model Parameters table in the device-specific data manual
TI Precision Labs training refers to this as "Csh"
Cp ADC pin parasitic capacitance Provided in the Per-Channel Parasitic Capacitance table in the device-specific data manual
CS (range) Range of source capacitance Obtain using Analog Engineer's Calculator: ADC SAR Drive.
TI Precision Labs training refers to this as "Cfilt"
RS (range) Range of source resistance Obtain using Analog Engineer's Calculator: ADC SAR Drive.
TI Precision Labs training refers to this as "Rfilt"
BWOPA ADC driver op-amp minimum bandwidth Obtain using Analog Engineer's Calculator: ADC SAR Drive.
Op-amp Selected Op-amp part number Record selected op-amp here
Voa_ss Steady state op-amp output voltage Generated from DC nodal analysis of the Voa node
Copy to Voa_ss before proceeding with other simulations
CS (final) Final source capacitance Final selected Cs from simulation.
TI Precision Labs training refers to this as "Cfilt"
RS (final) Final source resistance Final selected RS from simulation.
TI Precision Labs training refers to this as "Rfilt"
BWRsCs Filter bandwidth from CS and RS 1 / (2π⋅CS⋅RS )
Note: For proper settling, the filter bandwidth will be necessarily higher than the ½ the sampling frequency, thus the combination of CS and RS generally will not function as an anti-aliasing filter.
Verr Actual settling error Ensure Verr < Verrmax
Othwerwise, additional iteration on selection of Cs , Rs , or the driving amplifier is needed.