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  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Mechanism of ADC Input Settling
    2. 1.2 Symptoms of Inadequate Settling
      1. 1.2.1 Distortion
      2. 1.2.2 Memory Cross-Talk
      3. 1.2.3 Accuracy
      4. 1.2.4 C2000 ADC Architecture
    3. 1.3 Resources
      1. 1.3.1 TINA-TI SPICE-Based Analog Simulation Program
      2. 1.3.2 PSPICE for TI Design and Simulation Tool
      3. 1.3.3 TI Precision Labs - SAR ADC Input Driver Design Series
      4. 1.3.4 Analog Engineer's Calculator
      5. 1.3.5 Related Application Reports
      6. 1.3.6 PSpice for TI ADC Input Models
  4. 2Input Settling Design Steps
    1. 2.1 Select the ADC
    2. 2.2 Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
      1. 2.2.1 Select Type
      2. 2.2.2 Resolution
      3. 2.2.3 Csh
      4. 2.2.4 Full-Scale Range
      5. 2.2.5 Acquisition Time
      6. 2.2.6 Outputs
      7. 2.2.7 Math Behind the Calculator
    3. 2.3 Select an Op-Amp
    4. 2.4 Verify the Op-Amp Model
    5. 2.5 Build the ADC Input Model
      1. 2.5.1 Vin
      2. 2.5.2 Voa, Voa_SS, and Verror
      3. 2.5.3 Rs, Cs, and Vcont
      4. 2.5.4 Ch, Ron, and Cp
      5. 2.5.5 S+H Switch, Discharge Switch, tacq, and tdis
    6. 2.6 Refine RC Filter Values Via Simulation
    7. 2.7 Perform Final Simulations
    8. 2.8 Input Design Worksheet
  5. 3Example Circuit Design
    1. 3.1  Select the ADC
    2. 3.2  Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
    3. 3.3  Verify the Op-Amp Model
    4. 3.4  Build the ADC Input Model
    5. 3.5  Bias Point Analysis to Determine Voa_ss
    6. 3.6  Transient Analysis to Determine Voa_ss
    7. 3.7  Perform Initial Transient Analysis
    8. 3.8  Iterative Approach to Refine RC Filter Values
    9. 3.9  Perform Final Transient Analysis
    10. 3.10 Perform Final Transient Analysis
    11. 3.11 Further Refinement
    12. 3.12 Further Simulations
    13. 3.13 Completed Worksheet
  6. 4Working With Existing Circuits or Additional Constraints
    1. 4.1 Existing Circuits
      1. 4.1.1 Brief Overview of Charge Sharing
      2. 4.1.2 Charge Sharing Example
      3. 4.1.3 Additional Resources for Charge Sharing
    2. 4.2 Pre-Selected Op-Amp
      1. 4.2.1 Pre-Selected Op-Amp Example
    3. 4.3 Pre-Selected Rs and Cs Values
      1. 4.3.1 Analytical Solution for ADC Acquisition Time
      2. 4.3.2 Example Analytical Solution for ADC Acquisition Time
  7. 5Summary
  8. 6References

1.1 Mechanism of ADC Input Settling

To convert a sensed analog voltage to a digital conversion result, the ADC first must accurately capture the applied input voltage into its sample-and-hold circuit (S+H). As shown in Figure 1-1, this entails charging the internal ADC S+H capacitor (Ch) to within some acceptable tolerance (typically 0.5 LSBs) of the applied voltage within the configured acquisition window time (also referred to as the S+H time).

GUID-782E2FAB-BE74-48C6-A15B-284CE0287A55-low.gifFigure 1-1 Settling of the ADC S+H Capacitor

Quickly charging Ch to the applied voltage is complicated by the finite bandwidth and settling time of the external ADC driver circuit and by the settling time of the internal ADC S+H circuit. In Figure 1-1, the driver is shown as an op-amp (OPA320), which has a finite bandwidth, and the driver circuit also has intentionally placed source resistance (Rs) and intentionally placed source capacitance (Cs) which have a finite settling time determined by their RC time constant. Note that other circuit topologies are possible for driving the ADC, and these circuits may have additional components that need to be modeled to ensure appropriate settling time. These components could include unintentional parasitics such as the output impedance of a sensor or the effective source resistance of a voltage divider. Figure 1-1 also shows that the ADC has an internal parasitic switch resistance (Ron). This, along with Ch, provides an additional RC time constant that limits settling speed.