SPRACZ7 January   2022 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Abbreviations
  3. 2 Central Processing Unit (CPU)
  4. 3 Development Tools
    1. 3.1 Driver Library (Driverlib)
    2. 3.2 Embedded Application Binary Interface (EABI) Support
  5. 4 Package and Pinout
  6. 5 Operating Frequency and Power Management
  7. 6 Power Sequencing
  8. 7 Input Clock Options
  9. 8 Memory Map
  10. 9 Flash and OTP
    1. 9.1 Size and Number of Sectors
    2. 9.2 Flash Parameters
    3. 9.3 Flash Programming
    4. 9.4 Entry Point into Flash
    5. 9.5 Dual Code Security Module (DCSM) and Password Locations
    6. 9.6 OTP
  11. 10Boot ROM
    1. 10.1 Boot ROM Reserved RAM
    2. 10.2 Boot Mode Selection
    3. 10.3 Bootloaders
  12. 11Architectural Enhancements
    1. 11.1 Clock Sources and Domains
    2. 11.2 Watchdog Timer
    3. 11.3 Peripheral Interrupt Expansion (PIE)
    4. 11.4 Lock Protection Registers
    5. 11.5 General-Purpose Input/Output (GPIO)
    6. 11.6 External Interrupts
    7. 11.7 Crossbar (X-BAR)
  13. 12Peripherals
    1. 12.1 New Peripherals
      1. 12.1.1 Analog Subsystem Interconnect
      2. 12.1.2 Comparator Subsystem (CMPSS)
      3. 12.1.3 Control Law Accelerator (CLA)
    2. 12.2 Control Peripherals
      1. 12.2.1 Enhanced Pulse Width Modulator (ePWM)
      2. 12.2.2 Enhanced Capture Module (eCAP)
      3. 12.2.3 Enhanced Quadrature Encode Pulse Module (eQEP)
      4. 12.2.4 Sigma-Delta Filter Module (SDFM)
    3. 12.3 Analog Peripherals
      1. 12.3.1 Analog-to-Digital Converter (ADC)
    4. 12.4 Communication Peripherals
      1. 12.4.1 SPI
      2. 12.4.2 SCI
      3. 12.4.3 USB
      4. 12.4.4 I2C
      5. 12.4.5 CAN
  14. 13Configurable Logic Block (CLB)
  15. 14Device Comparison Summary
  16. 15References

12.2.1 Enhanced Pulse Width Modulator (ePWM)

The ePWM module on the F2837xD/S/07x devices remains functionally the same, and includes many enhancements. As a result, additional registers have been added, and the ePWM address space has been remapped for better alignment and usage. These enhancements include:

  • Counter Compare Sub-module – added counter compares CMPC and CMPD to allow Interrupts and ADC SOC events to be generated.
  • Action Qualifier Sub-module – added shadow loading of AQCTLA and AQCTLB registers to enable changes that must occur at the end of a period even when the phase changes. Additionally, shadow to active load on SYNC and Global Reload for the Action Qualifier Sub-module is supported.
  • Dead-Band Sub-module – added high resolution capability to dead-band RED and FED in half-cycle clocking mode. Includes features to enable both RED and FED on either PWM outputs. Increased dead-band with 14-bit counters. Dead-band/dead-band high-resolution registers are shadowed to allow dynamic configuration changes.
  • Event Trigger Sub-module – Interrupts and ADC start-of-conversion can now be generated on both the TBCTR == zero and TBCTR == period events. This feature enables dual edge PWM control. Additionally, the ADC start-of conversion can be generated from an event defined in the digital compare submodule. Enhanced pre-scaling logic is also implemented to issue interrupt requests and ADC SOC expanded up to every 15 events, to allow software initialization of event counters on SYNC event.
  • Trip-Zone Sub-module – independent flags have been added to reflect the trip status for each of the TZ sources. Also, changes have been made to the trip zone module to support certain power converter switching techniques, such as valley switching. Trip-zone TZ4 is sourced from an inverted EQEPxERR signal, TZ5 is connected to the system clock fail logic, and TZ6 is sourced from the EMUSTOP output from the CPU.
  • Digital Compare Sub-module – Addition of the digital compare submodule which enhances the event triggering and trip zone submodules by providing filtering, blanking and improved trip functionality to digital compare signals. Such features are essential for peak current mode control and for support of analog comparators. The Digital Compare Trip Select logic [DCTRIPSEL] has up to 12 external trip sources that are selected by the Input X-BAR logic. This is in addition to an ability to OR all of them, for up to 14 external and internal sources which are used to create the respective DCxEVTs. Blanking window filter register width is 16 bits, and the DCCAP functionality has been enhanced to provide more programming flexibility.
  • High-Resolution PWM – includes the ability to enable high-resolution period and duty cycle control on both ePWMxA and ePWMxB outputs.
  • Simultaneous Writes to TBPRD and CMPx Registers – allows writes to TBPRD, CMPA:CMPAHR, CMPB:CMPBHR, CMPC, and CMPD of any ePWM module to be tied to any other ePWM module, and also allows all ePWM modules to be tied to a particular ePWM module, if desired.
  • Shadow to Active Load on SYNC of TBPRD and CMP Registers – supports simultaneous writes of TBPRD and CMPA/B/C/D registers.
  • Delayed Trip Functionality – changes have been added to achieve dead-band insertion capabilities to support delayed trip functionality, which is needed for peak current mode control type applications. This has been accomplished by allowing comparator events to go into the Action Qualifier Submodule as a trigger event (Events T1 and T2). If comparator T1/T2 events are used to modify the PWM, changes to the PWM waveform will not take place immediately, but instead they will synchronize to the next TBCLK.
  • One Shot and Global Reload of Registers – allows one shot and global reload capability from shadow to active registers. This avoids partial reload conditions in, for example, multi-phase applications. It also allows programmable pre-scale of shadow to active reload events. Global Load can simplify ePWM software by removing interrupts and ensuring that all registers are loaded at the same time.
  • PWM SYNC Related Enhancements – sync scheme now includes two possible external PWM SYNCIN sources that feed into every third instance of ePWM modules (ex. ePWM1, ePWM4, ePWM7, and so forth). The sync scheme allows PWM SYNCOUT generation based on CMPC and CMPD events. These events can also be used for PWMSYNC pulse selection.