SPRAD12A July   2022  – February 2023 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P550SJ , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 SysConfig
  5. 3 Time-Base (TB) Submodule
    1. 3.1 Setting the Frequency
    2. 3.2 Applying a Phase Shift
    3. 3.3 Setting up the Synchronization (Sync) Scheme
  6. 4 Counter-Compare (CC) and Action-Qualifier (AQ) Submodules
    1. 4.1 Calculating the Duty Cycle
  7. 5 Deadband (DB) Submodule
    1. 5.1 Setting up Signal Pairs
  8. 6 Verifying the Output
    1. 6.1 Checking the Duty Cycle and Dead-Time Insertion
    2. 6.2 Checking the Phase Shift Applied
  9. 7 Trip-Zone (TZ) and Digital Compare (DC) Submodules
    1. 7.1 Drive Outputs Low for an ePWM Cycle Upon Trip Condition Set Through CMPSS
    2. 7.2 Drive Outputs Low Until Cleared Through Software Upon Trip Condition set Through GPIO
  10. 8 Event-Trigger (ET) Submodule
    1. 8.1 Setting Up Time-Base Interrupts
  11. 9 Global Load
    1. 9.1 Applying Global Loading and One-Shot Load Feature
    2. 9.2 Linking the ePWM Modules
    3. 9.3 Updating Action Qualifier Settings and Counter Compare Values Through Global Loading
  12. 10Summary
  13. 11References
  14. 12Revision History

6.1 Checking the Duty Cycle and Dead-Time Insertion

To begin, the positive duty of the dead-band is verified. The desired frequency is 400 kHz for EPWM1, EPWM2, and EPWM3. As seen in GUID-63979800-A180-4E36-A63C-DF48DD878B3D.html#GUID-D19DF68A-A5E6-4FDB-BC79-4460E5820DBC the period of the ePWM outputs should be 2.5 µsec. Based on GUID-63979800-A180-4E36-A63C-DF48DD878B3D.html#GUID-29E50045-301A-44BB-AEA3-7DF4C8552950, the TBPRD value is 125, meaning the time-base counter of the ePWM module counts from 0 to 125 and then back down to 0, since the counter mode is set to up-down. This yields a total of 250 counts over one period. Therefore, each count of the time-base counter is 10 nsec based on #GUID-51930023-77FF-45BA-A4DF-1BDE69E7A9FB.

Equation 18. T i m e   f o r   o n e   c o u n t   o f   t h e   t i m e   b a s e   c o u n t e r =   T P W M T B P R D * 2 =   2.5   μ s e c 250 = 10   n s e c

The counter compare values are set at 69. For the A output, when the time-base counter equals the counter compare while it is counting up, the output is set to go high. When the time-base counter is counting down and there is a match with the counter compare value, then the output is supposed to go low. However, the dead-band submodule has also been set up to incorporate dead-time in the output. As seen through GUID-B8AD9A13-19AA-4EAA-92F9-01A70D8A12F0.html#GUID-E3B6BF83-A17E-46D5-93A1-51EEE273148A, the DBRED and DBFED are set to 20 in order to have a dead-time of 200 nsec, shown in #GUID-10D9A881-1809-4DE9-9B87-7650541787EC. Therefore, for EPWMxA, the output does not go high when the time-base counter equals 69 (CMPA value), but rather 89 since there are 20 counts of dead-time inserted for the rising edge. #GUID-4B1F6A2F-D03B-4E38-A540-1311E7D63F7F shows how to calculate the duty cycle based on this information.

Equation 19. D u t y   C y c l e =   O N   T i m e O N   T i m e + O F F   T i m e
Equation 20. D u t y   C y c l e = T B P R D - C M P A + D B R E D + T B P R D - C M P A T B P R D * 2
Equation 21. D u t y   C y c l e = ( 125 - 89 ) + ( 125 - 69 ) T B P R D * 2 =   92 250 = 36.8   %

Putting it in terms of time, 92 * 10 nsec is 920 nsec, so the positive pulse width should be 920 nsec as seen in #GUID-1B838787-5392-461B-B64C-807A832CB5B7.

Figure 6-1 Scope Capture of the ePWM Output Positive Duty
Figure 6-2 Scope Capture of ePWM Output With Dead-Time Insertion