With an increasing requirement for higher efficiency in LLC topology, synchronous rectification is becoming a must-have. Traditionally, it is difficult for an MCU to handle a multi-phase synchronous rectification topology, given the complex timing between the primary and secondary side, and between phases. However, the flexible type-4 PWM is making it possible with C2000.

Figure 2-5 shows the PWM configuration of synchronized rectification (SR) MOS. Note SR is using a separate PWM module from the primary side, thus a new set of CMPAs and CMPBs could be used with new action qualifier events. In order to ensure the safe operation of SR FETs, SR FETs are set to switch off slightly earlier than primary side FETs by setting CMPA_S = CMPA_P-t₁ and CMPB_S= CMPB_P- t₁. Meanwhile, the corresponding SR should also switch on later than the primary side switch, thus an AHC mode is used to delay the rising edge of the original SR signal to generate the PWM of SRA and complementary SRB. Considering a dead-band is existing in primary-side PWM, the dead-band on the secondary side must be large enough to make sure the SRx does not switch earlier than the primary side:

DB_s>t₁+DB_p

To make the calculation easier, we could set t1= DB_p, thus:

DB_s>2*DB_p