Figure 3-2 represents a working condition where SR on time exceeds the resonant period LLC converter. If the PWM cycle actually crosses 2 PWM counter cycles, it may cause some disorder on PWM waveform when there is a huge frequency change.

When PWM frequency is lower than the resonant frequency of LLC, the on-time of SR switch needs to be limited. Otherwise, a reverse current would exist on SR MOS which would significantly influence the efficiency of the converter and even bring the converter to danger due to the reverse recovery of the body-diode.

The CLB module on Gen 3 C2000 devices makes it easy to achieve highly flexible PWM waveforms. CLB implementation of PWM on time limitation is shown in Figure 3-3.

In this design, a counter is configured to limit the maximum on time of SR PWM. The counter would start to count once it receives the SR PWM rising edge and generate a pulse (match 1) when it reaches the configured match value. The match value decides maximum on time by CLB clock counts.

In LUT0, match signal is ‘ORed’ with input 2, which is the falling edge of original SR PWM, which is then connected into FSM_0. By correctly configuring FSM. e0 (rising edge of original PWM) would be able to pull high the S0 of FSM_S0, and e1 (falling edge of original PWM OR counter 0 match signal) would be able to pull down S0. By doing this, the S0 became the refined PWM which would be pulled down if the on-time exceeds the maximum value. The waveform of CLB internal signal is shown in Figure 3-4.

Finally, FSM_S0 could be the CLB ouput through OUTLUT, and finally reflect back as PWM output by configuring CLB output MUX.

Figure 3-6 shows the waveform when the PWM cycle is changing from 3 µs to 15 µs while the maximum on-time is limited to 5 µs. As the waveform shows, the refined PWM is pulled down immediately when the on time reaches 5 µs, thus this feature could be leveraged to limit the reverse current on SR FET in LLC convert.