SPRT759A October   2023  – June 2024 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4.   Introduction
  5.   Overview of IEC 60730 and UL 1998 Classifications
    1.     C2000 Capability by Device Family
  6.   C2000 Safety Collateral
    1.     Getting Started
    2.     Functional Safety Manuals
    3.     Software Collateral
  7.   Implementing Acceptable Measures on C2000 Real-Time MCUs
    1.     Implementation Steps
    2.     Example Mapping
    3.     Additional Best Practices
  8.   Mapping Acceptable Control Measures to C2000 Unique Identifiers
    1.     Unique Identifier Reference
    2.     CPU Related Faults
    3.     Interrupt Related Faults
    4.     Clock Related Faults
    5.     Memory Related Faults
    6.     Internal Data Path Faults
    7.     Input/Output Related Faults
    8.     Communication, Monitoring Devices, and Custom Chip Faults
  9.   Glossary
  10.   References

Additional Best Practices

This document is focused on C2000 Unique IDs that specifically map to IEC 60730 and UL 1998 requirements. The device-specific safety manual includes additional information that may assist the system designer. Review of the following functional safety manual sections is highly recommended:

  • Suggestions For Improving Freedom from Interference
  • Suggestions for Addressing Common Cause Failures
  • Summary of Safety Features and Diagnostics
    • Fault avoidance techniques
    • Low/zero overhead hardware diagnostics
    • Tests of safety features and diagnostics.

Table 6 lists some examples. To determine additional best practices for your specific device family, refer to the device-specific functional safety manual.

Table 6 Example Additional Unique IDs of Interest
Example C2000 Unique ID (1) Description
Fault avoidance CLK14 Peripheral clock gating.
CPU6 Disable of JTAG port.
DMA9 Disabling of unused DMA trigger sources
FLASH3 (2) Bit multiplexing in flash memory array
RST2 Reset cause information
SRAM4 (2) Bit multiplexing in SRAM memory array
SYS1 (2) Multi-bit enable keys for control registers.
SYS2 Lock mechanism for control registers
SYS7 Peripheral soft reset (SOFTPRES).
Zero or low overhead / hardware feature CLK1 Missing clock detect
CPU8 Internal watchdog
CPU5 Access protection mechanism for memories
CPU14 Stack overflow detection
PIE7 Maintain interrupt handlers for unused interrupts
PWM8 ePWM fault detection using X-BAR
SYS8 EALLOW/MEALLOW protection for critical registers
Best practices / highly recommended PWR1 External voltage supervisor
CLK7 External watchdog
SRAM7 Data scrubbing to detect/correct memory errors
CLK10 Testing of a feature / diagnostic. CLK10, for example, is a software test of the watchdog operation.
(1) A safety feature or diagnostic may be referenced by multiple IDs. For example, CPU5 is also CLA9, SRAM11, and DMA8 along with other IDs. This table only lists one of the IDs for simplicity.
(2) Enabled by default and cannot be disabled.