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Many battery-powered products such as wireless security cameras, video doorbells, and smart locks, are designed to have the option of running entirely off battery power, or with a battery and no other input power alternative. This allows users to install devices in any place of their choosing, regardless of the availability of a power socket nearby, and provide a more complete and discrete security coverage of their home.
Two challenges faced in the design of the system are reducing the amount of power lost in the power tree itself, and generating the power rails with minimal noise to meet peripheral input voltage noise requirements and improve performance. For example, a wireless security camera powered with two AA batteries requires less than 127 µA average system current (including both power-on and standby modes) to achieve two years of battery life. This can be calculated for any battery capacity and desired lifetime using Equation 1, which uses a 30% safety margin for the total battery capacity.
To achieve longer battery life, wireless or battery-powered cameras require a very low quiescent current (IQ) and high efficiency at both full and light loads. These cameras typically employ motion detection, human interface, wireless communications monitoring, or any combination of the three to minimize time spent in power-hungry states. Because most of the device lifetime is spent in low-power states, quiescent currents, subsystem shutdown currents, and high efficiency are very important, as these standby currents can have significant impacts on overall battery life.
High voltage accuracy on the power rails is also a requirement, especially on rails that are powering core supply voltages, high speed I/O lines, and analog supplies. For HD video processing and streaming, the MPU is clocked at a very high speed, and employs a strict jitter budget. A noisy power supply to these high-speed lines induces jitter, thereby increasing bit error rate and degrading the quality of the high-speed signal. One example of this requirement is on the image sensor analog voltage, where it is necessary to ensure power supply noise is minimized to achieve a very high contrast ratio.
This document explores three different architectures for implementing high-efficiency, low-ripple buck converters for a battery-powered application, and the trade-offs for each. Possible solutions shown include: buck converter + LDO, forced pulse width modulation (FPWM) buck converter, and buck converter + PI filter. The performance of each is evaluated with respect to output voltage ripple, system efficiency at full and light loads, and IQ.
Architecture A is implemented with the buck converter TLV62568 and the LDO TPS7A05.
TLV62568 is a high-efficiency, cost-effective buck converter utilizing an adaptive off-time with peak current control topology. The device operates at typically 1.5-MHz frequency PWM at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and load current. The current of the high-side switch is sensed for peak current control, and implements a switch current limit to prevent the device from drawing excessive current from a battery, or input voltage rail. Once the high-side switch current limit is reached, the high-side switch is turned off, and the low-side switch is turned on to ramp down the inductor current with an adaptive off-time.
TPS7A05 is an ultra-small, low quiescent current LDO that can source 200 mA with excellent transient performance. This device has an output range of 0.8 V to 3.3 V with a typical 1% accuracy. This LDO offers foldback current limit, shutdown, and thermal protection.
Architecture B is implemented with the FPWM version of the same buck converter from Architecture A, TLV62568A. As such, the control topology and functionality are essentially the same,but with the difference of TLV62568A staying in PWM mode at light loads while the TLV62568 goes into pulse frequency modulation (PFM) operation at light loads.
Architecture C is implemented with buck converter TPS62841, which has an ultra-low nominal IQ of 60 nA, high light-load efficiency, and utilizes DCS-Control™. DCS–Control is a high-performance control scheme that combines the advantages of hysteretic and voltage mode controls. This combination allows for excellent AC load regulation and transient response, low output ripple voltage, and a seamless transition between PFM and PWM modes with minimum output voltage ripple. It includes an AC loop that senses the output voltage and directly feeds this information into a fast comparator stage. An additional voltage feedback loop is used to achieve accurate DC load regulation, and an internally compensated regulation network achieves fast and stable operation with small, external components and low ESR capacitors. In PFM, or Power-Save Mode, the switching frequency varies linearly with the load current.
Architecture A: Buck Converter + LDO
The first architecture to be discussed is a common solution, where a buck converter is followed by an LDO to reduce output voltage ripple in order to meet required output voltage accuracy.
The benefit of using this topology is that this solution keeps noise on sensitive rails low compared to a buck converter alone, due to the power supply rejection ratio (PSRR) of the LDO. When several LDOs are cascaded off a single buck converter to create multiple power rails, there is an added benefit.The magnitude of rejection, and the frequency of the output voltage ripple,are almost the same since there is only one switching converter sourcing the rails, rather than multiple switching converters sourcing the rails. With multiple switching converters, there is no correlation between output voltage frequency and magnitude, while the PSRR of an LDO is constant at a particular switching frequency and adds no switching elements.
One thing worth noting when designing with this topology is the noise-filtering capability of the LDO. An LDO with high PSRR can be chosen for noise-sensitive rails. However, this PSRR changes with respect to the switching frequency and output current. Figure 3-2 shows an example of this for the TPS7A05, the LDO used in Architecture A. In general, an LDO has better noise attenuation at lower switching frequencies, (such as when the converter is in PFM operation) and worse noise attenuation at higher switching frequencies (such as when the converter is operating at nominal switching frequency). This being said, the PSRR at high frequencies can be improved by increasing the output capacitor value.
One other thing to be aware of is the efficiency of the LDO, which can be calculated as shown in Equation 2. With higher voltage drop comes lower system efficiency, causing the power tree to draw more current from the battery at all load levels and ultimately decrease the battery life. As shown in Equation 3 and Equation 4, higher voltage drop also causes a higher temperature within the LDO IC itself, which is something to be especially aware of in designs that need to meet outdoor operating temperature requirements.
One other LDO to consider for use with this architecture is the TPS7A02, which has an ultra-low nominal IQ of 25 nA, even in dropout. TPS7A02 is also optimized for excellent transient performance, and features a smart enable circuit with an internally controlled pulldown resistor to help minimize the external components used to pulldown the enable pin.
Architecture B: FPWM Buck Converter
The second architecture is a simple solution for applications concerned with noise. An efficient switching converter is forced to stay in PWM mode at light loads, rather than enter the power-saving PFM mode. In PFM mode, the converter only operates in short bursts when the output voltage falls below the nominal output voltage. This saves power by only turning on and switching when the minimum output voltage threshold is crossed, which reduces switching losses.
For buck converters that operate in both PFM and PWM modes, varying ripple voltage and frequency can be seen in dynamic load conditions as the buck converter changes operating mode from PFM to PWM, or vice versa. This behavior is not seen in the FPWM device, as it is forced to stay in PWM mode regardless of the load applied. As such, the benefit of a FPWM buck converter is that the switching frequency does not change, giving a fairly constant ripple for a fixed output capacitor, and improving the transient response across load variations. Additionally, the system efficiency at full load is much higher than the previous cascaded architecture, since no LDO is present.
The disadvantage of this architecture is a high IQ and low light-load efficiency. Both of these disadvantages are direct results of the FPWM mode. Because the device remains in PWM mode regardless of the load conditions, the device continues to switch at high frequency and draw higher current even at no load, which causes a high IQ. For the same reason, the light-load efficiency is extremely low since the current drawn by the buck converter is much higher than the output current at light loads.
Architecture C: Buck Converter + PI Filter
The third and final architecture to be discussed is a high-performance solution where a noise-sensitive rail is powered by an efficient switching converter to generate the desired voltage. As shown in Figure 3-4, it is followed by a ferrite bead PI filter to attenuate the switching noise. In this configuration, the buck converter can operate in the power-saving PFM mode, which allows for higher efficiency in light load conditions as previously discussed.
Implementing this architecture results in the lowest and most consistent output voltage ripple for full load conditions, which makes it the most ideal for peripherals with tight power supply noise requirements. Because these peripherals have the most stringent power supply regulation requirements when they are powered and actively processing data, full load noise levels are more important than light load noise levels, as light loads typically correspond to a peripheral in standby or shutdown mode.
In addition to low noise, this architecture provides high efficiency at all load levels. Similar to Architecture B, this topology is comprised of a single buck converter and no LDO, so the system efficiency is much higher than a power architecture using one or more LDOs. Unlike Architecture B, the noise requirement is handled externally by the buck converter with a PI filter, which allows the converter to operate in PFM mode and increases efficiency in light load conditions.
There are some considerations to take in the process of designing with this architecture. It is necessary to calculate the frequency and magnitude of the output voltage ripple of the buck converter for operating load conditions of the peripherals in order to design the PI filter, and there are further calculations in choosing the ferrite bead and passives around it. Implementing the PI filter is not quite as simple as implementing an LDO, which requires choosing an adequate PSRR at the nominal switching frequency of the buck converter. Additionally, the PI filter has a more limited bandwidth for rejection, and has slight variations in settling time, which is a function of the filter values.
For this design, a ferrite bead is used and the following values chosen for the PI filter:
The PI filter design is done using equations and criteria from TIDA-01579.Figure 3-5 shows the filter circuit and the equivalent circuit of the ferrite bead.