Achieve Delayed Protection for Three-Level Inverter With Type 4 EPWM

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

Figure 1-1 shows a typical single phase three-level I-Type inverter, named neutral point clamped (NPC) inverter. The single phase NPC inverter includes 4 FETs, like IGBT, in series, where S1 and S4 are called outer switches, with S2 and S3 called inner switches.

Figure 1-1 Single Phase Three-Level I-Type Inverter

Considering the difference between positive cycle and negative cycle when tied to the grid, the general switching states of four FETs in normal operation are shown in Table 1-1.

Table 1-1 General Switching States in Normal Operation

Symbol	Switching states
Symbol	S1	S2	S3	S4
Positive	Alternate switch	Remaining ON	Alternate switch	Remaining OFF
Negative	Remaining OFF	Alternate switch	Remaining ON	Alternate switch

There are several events which lead to quick shut-down to protect the semiconductors and the system, like over current, thermal overload, etc. Unlike immediately switching off all the FETs simultaneously in two level inverter, for three-level inverter, it must be made sure that the correct switch-off sequence is maintained: outer switches (S1 or S4) off first, inner switches (S2 or S3) off after a specific delay, while the inner one must be switched on firstly during the recover process. This delayed protection requirement has been a challenge for lots of UPS or solar inverter customers for a long time. Since using software algorithms will cause too much delay to provide in-time protection, some customers have to use external hardware circuits, like FPGA or CPLD, to achieve such protection logic, which increases the system cost and also the development effort.

This application report demonstrates how to implement delayed protection with existed Type 4 ePWM features that are available in all new C2000 devices, including F2838xD/S, F2837xD/S, F2807x and F28004x. In the Type 4 EPWM module, the Action Qualifier sub-module includes two additional trigger events (T1 and T2), which can be sourced from comparator, trip or sync events, together with Dead-Band sub-module, make it possible to add customized delay time to tripped/fault signals.

2 Implementation Guidance

2.1 Expected Results Overview

Figure 2-1 shows the expected EPWM protection results during positive and negative cycle operation conditions. In the given example, EPWM1A/2B/1B/2A are used for S1/2/3/4 control, respectively. And an extra EPWM output, EPWM7A in the example, is required to support the delayed protection logic. The trip signal is simulated and generated with an EPWM output, EPWM8A here, for the quick validation purpose.

Take the positive cycle operation as example, whenever the trip event occurs, EPWM1A and EPWM1B, which are configured with cycle-by-cycle tripping (CBC) action, are shut down immediately, while EPWM2B will be forced down after a Trip delay. Besides, when trip event disappears, EPWM2B will turn high immediately, which is also aligned with the basic recover requirement.

Figure 2-1 Expected EPWM Protection Results During Positive and Negative Cycle Operation Conditions

Note that the given example code is based on F28004x, and it can be easily migrated to any other C2000 devices with Type 4 EPWM. And the code, built with the Driverlib API format, makes it more flexible to change or add the selected EPWM modules for different FET controls. Though the example is designed for single phase three-level inverters, the same configuration method can be used for three phase inverter topology, with six EPWM modules for main FETs control and one auxiliary EPWM channel needed. The example project discussed in this application report is available in the latest C2000WARE-DIGITALPOWER-SDK, navigating to the directory C:\ti\c2000\C2000Ware_DigitalPower_SDK_X_XX_XX_XX\libraries\3_level_inv_delayed_protection_scheme\examples.