DLPT030 February   2023 DLP6500FLQ , DLP650LNIR , DLP7000 , DLP7000UV , DLP9000X , DLP9000XUV , DLP9500 , DLP9500UV , DLPC410 , DLPC910

 

  1.   Abstract
  2. 1Affected Products
  3. 2Master Serial Peripheral Interface Flash Configuration Method
  4. 3SPI Flash Configuration Method
    1. 3.1 Configuration Guide
    2. 3.2 FPGA Pinout Information
    3. 3.3 Design Details Supporting SPI Flash Configuration Method
    4. 3.4 SPI Flash Layout Connections
    5. 3.5 Approved SPI PROMs
      1. 3.5.1 Current List of AMD Xilinx Approved SPI Flash for Virtex-5
      2. 3.5.2 Xilinx Support Forum
  5. 4Common Question and Answers
  6. 5Revision History

3.4 SPI Flash Layout Connections

The DLPC910 and DLPC410 Controllers must be connected to SPI Flash using the connections described in the diagram below

.

GUID-20230112-SS0I-BV6J-QFBS-NVZMBFVMMF35-low.jpg

SPI Flash Write Protect (WP#) should be pulled high to allow for programming through the Virtex 5 JTAG interface. SPI Flash Reset (RESET#) or Hold (HOLD#) should be pulled high to prevent the SPI Flash from pausing serial communications with the DLPC410 and DLPC910 controllers.

For additional details on how the SPI Configuration Flash is connected to the DLPC410 Controller and DLPC910 Controller, please refer to the schematics for the DLPLCRC910EVM and DLPLCRC410EVM.

  • FCS_B = pin AA10 of DLPC910 Controller and DLPC410 Controller
  • MOSI = pin AA9 of DLPC910 Controller and DLPC410 Controller
  • CCLK = pin J10 of DLPC910 Controller and DLPC410 Controller
  • D_IN = pin K11 of DLPC910 Controller and DLPC410 Controller