SBAA535A March   2022  – March 2024 ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1013-Q1 , ADS1014 , ADS1014-Q1 , ADS1015 , ADS1015-Q1 , ADS1018 , ADS1018-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1113-Q1 , ADS1114 , ADS1114-Q1 , ADS1115 , ADS1115-Q1 , ADS1118 , ADS1118-Q1 , ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS1146 , ADS1147 , ADS1148 , ADS1148-Q1 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1216 , ADS1217 , ADS1218 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS1243-HT , ADS1246 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS1281 , ADS1282 , ADS1282-SP , ADS1283 , ADS1284 , ADS1287 , ADS1291 , LMP90080-Q1 , LMP90100 , TLA2021 , TLA2022 , TLA2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Data Sheet Timing and Nomenclature
  6. 3 What Causes Conversion Latency in a Delta-Sigma ADC?
  7. 4 Digital Filter Operation and Behavior
    1.     8
    2.     9
    3. 4.1 Unsettled Data Due to an ADC Operation
  8. 5 ADC Features and Modes that Affect Conversion Latency
    1. 5.1 First Conversion Versus Second and Subsequent Conversion Latency
    2. 5.2 Conversion Mode
    3. 5.3 Programmable Delay
    4. 5.4 ADC Overhead Time
    5. 5.5 Clock Frequency
    6. 5.6 Chopping
  9. 6 Analog Settling
  10. 7 Important Takeaways
  11. 8 Cycle Time Calculation Examples
    1. 8.1 Example #1: Using the ADS124S08
    2. 8.2 Example #2: Changing the Conversion Mode
    3. 8.3 Example #3: Changing the Filter Type
    4. 8.4 Example #4: Changing the Clock Frequency
    5. 8.5 Example #5: Enabling Chop and Reducing the Number of Conversions per Channel
    6. 8.6 Example #6: Scanning Two Channels With Different System Parameters
    7. 8.7 Example #7: Using the ADS1261
    8. 8.8 Example #8: Changing Multiple Parameters Using the ADS1261
  12. 9 Summary
  13. 10Revision History

8.7 Example #7: Using the ADS1261

Table 8-8 reports the system parameters that determine the cycle time in Example #7:

Table 8-7 System Parameters for Example #7
PARAMETERVALUE
ADCADS1261
ODR4800 SPS
Filter typesinc4
Clock frequency7.3728 MHz (default)
Conversion modeContinuous
Programmable delay50 μs (default)
ChoppingDisabled
Conversions per channel3
# of channels2

Unlike the previous examples that used the ADS124S08, Example #7 uses the ADS1261. Consequently, the default clock frequency and programmable delay time are different, as are the ODR and filter type options. However, the process for determining the cycle time remains the same.

Refer to Table 2-2 to identify the ADS1261 first conversion latency, tFC, using the sinc4 filter and ODR = 4800 SPS. This is given as 1.258 ms and includes the default programmable delay time of 50 µs as well as any ADC overhead. Second and subsequent conversion latency, tSSC, is not provided directly in the ADS1261 data sheet. Instead, the Conversion Latency section in the ADS1261 data sheet states that tSSC = 1 / ODR when continuous conversion mode is used and chop is disabled. Since both of these conditions are true for this example, tSSC is given by Equation 32:

Equation 32. tSSC = 1 / ODR = 1 / 4800 = 0.208 ms

Finally, there is no need to consider additional latency due to chopping. Equation 34 calculates the cycle time, tCYCLE, using the scan time for one channel, tCH, that results from Equation 33:

Equation 33. tCH = 1 ∙ tFC + 2 ∙ tSSC = 1 ∙ 1.258 ms + 2 ∙ 0.208 ms = 1.674 ms
Equation 34. tCYCLE = # of channels ∙ tCH = 2 ∙ 1.674 ms = 3.348 ms

Ultimately, the cycle time for this example is 3.348 ms for 6 conversion results. Figure 8-8 depicts a timing diagram for the example system given the design parameters.

GUID-20220201-SS0I-8N8L-6QGB-C7Z9JNQFHQHF-low.svgFigure 8-8 Timing Diagram for Example #7