SBAA535A March   2022  – March 2024 ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1013-Q1 , ADS1014 , ADS1014-Q1 , ADS1015 , ADS1015-Q1 , ADS1018 , ADS1018-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1113-Q1 , ADS1114 , ADS1114-Q1 , ADS1115 , ADS1115-Q1 , ADS1118 , ADS1118-Q1 , ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS1146 , ADS1147 , ADS1148 , ADS1148-Q1 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1216 , ADS1217 , ADS1218 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS1243-HT , ADS1246 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS1281 , ADS1282 , ADS1282-SP , ADS1283 , ADS1284 , ADS1287 , ADS1291 , LMP90080-Q1 , LMP90100 , TLA2021 , TLA2022 , TLA2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Data Sheet Timing and Nomenclature
  6. 3 What Causes Conversion Latency in a Delta-Sigma ADC?
  7. 4 Digital Filter Operation and Behavior
    1.     8
    2.     9
    3. 4.1 Unsettled Data Due to an ADC Operation
  8. 5 ADC Features and Modes that Affect Conversion Latency
    1. 5.1 First Conversion Versus Second and Subsequent Conversion Latency
    2. 5.2 Conversion Mode
    3. 5.3 Programmable Delay
    4. 5.4 ADC Overhead Time
    5. 5.5 Clock Frequency
    6. 5.6 Chopping
  9. 6 Analog Settling
  10. 7 Important Takeaways
  11. 8 Cycle Time Calculation Examples
    1. 8.1 Example #1: Using the ADS124S08
    2. 8.2 Example #2: Changing the Conversion Mode
    3. 8.3 Example #3: Changing the Filter Type
    4. 8.4 Example #4: Changing the Clock Frequency
    5. 8.5 Example #5: Enabling Chop and Reducing the Number of Conversions per Channel
    6. 8.6 Example #6: Scanning Two Channels With Different System Parameters
    7. 8.7 Example #7: Using the ADS1261
    8. 8.8 Example #8: Changing Multiple Parameters Using the ADS1261
  12. 9 Summary
  13. 10Revision History

8.3 Example #3: Changing the Filter Type

Table 8-8 reports the system parameters that determine the cycle time in Example #3:

Table 8-3 System Parameters for Example #3
PARAMETERVALUE
ADCADS124S08
ODR1000 SPS
Filter typeLow-latency
Clock frequency4.096 MHz (default)
Conversion modeSingle-shot
Programmable delay14 ∙ tMOD (default)
ChoppingDisabled
Conversions per channel3
# of channels2

Example #3 keeps all of the same system parameters as Example #2 with the exception of switching to the ADS124S08 low-latency filter. This choice reduces the conversion latency for each first conversion.

While not shown in this document, the ADS124S08 data sheet identifies the first-conversion latency, tFC, using the low-latency filter at ODR = 1000 SPS as 1.156 ms. This time assumes that the default clock frequency, fCLK, of 4.096 MHz is used, which is the case for this example. Also, this time includes the ADC overhead but does not include the programmable delay, tDELAY. Equation 14 calculates the value of tDELAY in microseconds using the default value of tDELAY = 14 ∙ tMOD and fCLK = 4.096 MHz:

Equation 14. tDELAY = 14 ∙ tMOD = 14 ∙ (16 / fCLK) = 54.69 µs

The ADS124S08 programmable delay applies to each conversion using single-shot mode, resulting in a first conversion latency including programmable delay, tFC_TOTAL, as per Equation 15:

Equation 15. tFC_TOTAL = tFC + tDELAY = 1.156 ms + 0.055 ms = 1.211 ms

Finally, there is no need to consider additional latency due to chopping. Since all three conversions use single-shot mode and therefore are subject to tFC_NEW, the scan time for one channel, tCH, is given by Equation 16. This assumes that the user starts the next conversion on each channel immediately after the previous conversion result is ready:

Equation 20. tCH = 3 ∙ tFC_TOTAL = 3 ∙ 1.211 ms = 3.633 ms

Equation 17 calculates the cycle time, tCYCLE, using the result from Equation 16:

Equation 17. tCYCLE = # of channels ∙ tCH = 2 ∙ 3.633 ms = 7.266 ms

Ultimately, the cycle time for this example is 7.266 ms for 6 conversion results. Figure 8-3 depicts a timing diagram for the example system given the design parameters.

GUID-20220201-SS0I-V1BT-JWN9-ZWLK939KSS7M-low.svgFigure 8-3 Timing Diagram for Example #3