Table 8-6 reports the system parameters that determine the cycle time in Example #6:

Example #6 introduces different parameters for each of the two channels. This requires analyzing CH1 and CH2 separately to determine their respective scan times, t_CH1 and t_CH2.

To determine t_CH1, consider that the ADC is operating at 800 SPS, the low-latency filter is used, the ADC is operating in continuous-conversion mode, the default programmable delay has been selected, and chop is enabled. Additionally, this system does not use the default clock frequency, f_CLK, of 4.096 MHz. Instead, it is necessary to accommodate a new clock frequency, f_{CLK_NEW}, of 4.5 MHz.

First, identify the first conversion latency for CH1, t_{FC_CH1}, using the ADS124S08 low-latency filter at 800 SPS. Even though continuous-conversion mode is used for CH1, second and subsequent conversion latency does not apply because global chop is enabled. While not shown in this document, the ADS124S08 data sheet identifies that t_{FC_CH1} = 360 ∙ t_MOD periods using the low-latency filter at ODR = 800 SPS. Using the conversion latency in terms of t_MOD periods instead of milliseconds enables easier calculations because the number of t_MOD periods is independent of clock frequency.

The time specified by t_{FC_CH1} includes the ADC overhead but does not include the programmable delay, t_DELAY. Using the default value of t_DELAY = 14 ∙ t_MOD, the total first conversion latency for CH1, t_{FC_CH1_TOTAL}, is given by Equation 26:

Next, Equation 27 calculates one t_MOD period in terms of f_{CLK_NEW} using the ADS124S08:

At f_{CLK_NEW} = 4.5 MHz, t_MOD = 3.56 µs. Therefore, t_{FC_CH1_TOTAL} = 374 ∙ 3.56 µs = 1.331 ms.

As described in Section 5.6, each conversion result when global chop is enabled is an average of two conversions. Producing the data for each conversion requires 1 ∙ t_{FC_CH1_TOTAL} due to input swapping, and therefore the first conversion result with global chop enabled requires 2 ∙ t_{FC_CH1_TOTAL}. However, in continuous conversion mode, the previous conversion can be averaged with the next conversion to generate the second conversion result. This second conversion result is therefore only subject to 1 ∙ t_{FC_CH1_TOTAL}. Figure 8-6 shows how this behavior affects the conversion latency for each conversion result from CH1.

Figure 8-6 Timing Diagram for CH1 in Example #6

Figure 8-6 reveals that the scan time for CH1, t_CH1, is given by Equation 28:

Note that CH1 only yields two conversion results even though t_CH1 is comprised of 3 ∙ t_{FC_CH1_TOTAL}. This is specifically due to global chop being enabled and operating in continuous-conversion mode.

To determine t_CH2, consider that the ADC is sampling at 200 SPS, the sinc³ filter is used, the ADC is operating in single-shot conversion mode, the programmable delay is 256 ∙ t_MOD, and chop is disabled. Additionally, the same clock frequency from CH1 is used for CH2, where f_{CLK_NEW} = 4.5 MHz.

First, Table 5-1 identifies that the first conversion latency for CH2, t_{FC_CH2}, is equal to 3905 ∙ t_MOD periods using the ADS124S08 sinc³ filter at 200 SPS. Using the conversion latency in terms of t_MOD periods instead of milliseconds enables easier calculations because the number of t_MOD periods is independent of clock frequency.

The time specified by t_{FC_CH2} includes the ADC overhead but does not include t_DELAY. Using the example value of t_DELAY = 256 ∙ t_MOD, the total first conversion latency for CH2, t_{FC_CH2_TOTAL}, is given by Equation 29:

Therefore, t_{FC_CH2_TOTAL} = 4161 ∙ 3.56 µs = 14.813 ms because t_MOD was calculated to be 3.56 µs for CH1 when f_{CLK_NEW} = 4.5 MHz. Additionally, the use of single-shot conversion mode means that all three conversion results required by CH2 are subject to first conversion latency. Assuming that the user starts the next conversion on CH2 immediately after the previous conversion result is ready, Equation 30 calculates t_CH2:

Finally, there is no need to consider additional latency for CH2 due to chopping. Equation 31 calculates the cycle time, t_CYCLE, by summing the scan time for each channel:

Ultimately, the cycle time for this example is 48.432 ms for 5 conversion results. Figure 8-7 depicts a timing diagram for the example system given the design parameters.

Figure 8-7 Complete Timing Diagram for Example #6