Clock Edge Delay Compensation With Isolated Modulators Digital Interface to MCUs
Abstract
Isolated Delta-Sigma modulators such as AMC1306M25 with high-speed digital interface are commonly used for accurate, low latency and high noise immunity shunt-based phase current sensing in servo drives and robotics applications. Especially at higher clock frequencies, proper routing, termination, and compliance with the corresponding MCU’s setup and hold timings are critical for a reliable operation. A commonly used method and compromise to meet the MCU timing requirements is to reduce the modulator clock frequency, which also reduces the data output rate. This application note shows more designed for clock edge compensation methods to meet the setup and hold timing requirements up to the maximum clock rate of the modulator. This enables the system to operate at maximum data rate. The application note outlines options for clock edge compensation and shows example measurements with TI’s isolated modulators AMC130x connected to C2000™ and Sitara™ MCUs. In addition, a calculation tool is provided to validate the digital interface timing.
Trademarks
C2000™, Sitara™, OSR™, and Code Composer Studio™ are trademarks of Texas Instruments.
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1 Introduction
Isolated Delta-Sigma Modulators are commonly used for shunt-based phase current sensing in servo drives and robotics applications as accurate and low latency isolated phase current sensing has a significant impact on the performance of three-phase inverters. Delta-Sigma modulators provide a digital bit stream with either LVDS or CMOS interface to an MCU that allows for exceptional noise immunity, high precision, and low latency phase current measurement. For additional information on isolated modulators, please see Comparing Isolated Amplifiers and Isolated Modulators, application note.
Often the shunts and the isolated Delta-Sigma modulators are placed on the power stage printed circuit board (PCB), while the MCU is placed on a separate control board PCB, as shown in figure 1. Proper routing schemes on the PCBs and the interface connector are crucial for digital signal integrity. Best practices for clock and data line routing and termination are discussed in Better Signal Integrity w/ Isolated Delta-Sig. Modulators in Motor Drives (ti.com), application report.
Figure 1-1 Simplified 3-Phase Inverter Block Diagram With Digital Interface From MCU to Isolator Modulators There can be further design challenges to meet the timing between the modulator clock edge and the digital bitstream, especially when the signal traces are quite long, additional buffers and level translators are used. Then an additional propagation delay of the modulator clock and bitstream signal can even force designers to reduce the modulator clock from the maximum 21 MHz (AMC1306) to e.g. 15 MHz to meet the timing between clock edge and bitstream data at the MCU. Due to that the overall phase current measurement latency increases reverse proportional to the selected modulator clock. For example, a typically used Sinc3 decimation filter with an oversampling ratio of 64 has a measurement latency (propagation delay) of 4.8us at 20 MHz modulator clock, while the latency increases to 6.4us when only a 15 MHz modulator clock can be used.
The following sections of this document provide an overview of digital timing compensation methods to overcome this design challenge and show that designing with an isolated modulator offers not only the highest precision measurement but also the easiest.
