SBAA607A December   2023  – January 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P4 , AM263P4-Q1 , AMC1303M2520 , AMC1305L25 , AMC1306M25 , F29H850TU , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Challenge With Digital Interface Timing Specifications
  6. 3Design Approach With Clock Edge Delay Compensation
    1. 3.1 Clock Signal Compensation With Software Configurable Phase Delay
    2. 3.2 Clock Signal Compensation With Hardware Configurable Phase Delay
    3. 3.3 Clock Signal Compensation by Clock Return
    4. 3.4 Clock Signal Compensation by Clock Inversion at the MCU
  7. 4Test and Validation
    1. 4.1 Test Equipment and Software
    2. 4.2 Testing of Clock Signal Compensation With Software Configurable Phase Delay
      1. 4.2.1 Test Setup
      2. 4.2.2 Test Measurement Results
    3. 4.3 Testing of Clock Signal Compensation by Clock Inversion at MCU
      1. 4.3.1 Test Setup
      2. 4.3.2 Test Measurement Results
        1. 4.3.2.1 Test Result – No Clock Inversion of Clock Input at GPIO123
        2. 4.3.2.2 Test Result – Clock Inversion of Clock Input at GPIO123
    4. 4.4 Digital Interface Timing Validation by Calculation Tool
      1. 4.4.1 Digital Interface With No Compensation Method
      2. 4.4.2 Commonly Used Method - Reduction of the Clock Frequency
      3. 4.4.3 Clock Edge Compensation With Software Configurable Phase Delay
  8. 5Conclusion
  9. 6References
  10. 7Revision History

3.4 Clock Signal Compensation by Clock Inversion at the MCU

The last method for clock signal compensation is clock inversion at the MCU and works for Delta-Sigma modulators with external and internal clock source. In that case, the selected MCU must be capable of inverting the GPIO input. The TMS320F28379D GPIO inputs prior to the SDFM (Sigma Delta Filter Module) can be configured to invert the input signal at any GPIO, as shown in Figure 3-5. For example, the clock input signal is inverted at GPIO123, hence the SD1_C1 clock signal is inverted versus the AMC1303Mx clock signal. As a result, the SDFM samples the input data SD1_D1 versus the falling edge of the external clock signal at the input of GPIO123, as shown in Figure 3-6.

GUID-20231128-SS0I-XDMV-JWGC-KRG4PRHTNMWZ-low.svg Figure 3-5 TMS320F28379D SDFM/GPIO Block Diagram
GUID-20231128-SS0I-NB7R-3PQH-4ZTXD4RTXKHT-low.svg Figure 3-6 TMS320F28379D SDFM Timing With Inverted Clock at GPIO123

By inverting the clock input signal by using the GPIO a fixed delay of one-half of the clock period is added to the clock signal. Depending on the timing specifications and propagation delays of the system setup, this additional delay may be sufficient to meet the TMS320F28379D setup and hold timings of minimum 10 ns for the SDFM qualified GPIO (3-sample) mode 0. However, as this clock signal compensation method’s additional delay time is fixed and cannot be changed, it must be verified for each system design that the resulting timings for setup and hold of the MCU for the SDFM qualified GPIO (3-sample) mode 0 are met.

This compensation method is also applicable to Sitara MCUs, where both the rising and falling edges of the external clock signal can be set as data acquisition point by software.