SBAA607A December   2023  – January 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P4 , AM263P4-Q1 , AMC1303M2520 , AMC1305L25 , AMC1306M25 , F29H850TU , F29H859TU-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Challenge With Digital Interface Timing Specifications
  6. 3Design Approach With Clock Edge Delay Compensation
    1. 3.1 Clock Signal Compensation With Software Configurable Phase Delay
    2. 3.2 Clock Signal Compensation With Hardware Configurable Phase Delay
    3. 3.3 Clock Signal Compensation by Clock Return
    4. 3.4 Clock Signal Compensation by Clock Inversion at the MCU
  7. 4Test and Validation
    1. 4.1 Test Equipment and Software
    2. 4.2 Testing of Clock Signal Compensation With Software Configurable Phase Delay
      1. 4.2.1 Test Setup
      2. 4.2.2 Test Measurement Results
    3. 4.3 Testing of Clock Signal Compensation by Clock Inversion at MCU
      1. 4.3.1 Test Setup
      2. 4.3.2 Test Measurement Results
        1. 4.3.2.1 Test Result – No Clock Inversion of Clock Input at GPIO123
        2. 4.3.2.2 Test Result – Clock Inversion of Clock Input at GPIO123
    4. 4.4 Digital Interface Timing Validation by Calculation Tool
      1. 4.4.1 Digital Interface With No Compensation Method
      2. 4.4.2 Commonly Used Method - Reduction of the Clock Frequency
      3. 4.4.3 Clock Edge Compensation With Software Configurable Phase Delay
  8. 5Conclusion
  9. 6References
  10. 7Revision History

3 Design Approach With Clock Edge Delay Compensation

To meet and further optimize the MCUs setup and hold timing requirements for reliable data acquisition, clock edge delay compensation is recommended. Clock edge delay compensation can be implemented by various methods, summarized below and expanded upon in the following section:

  1. Additional clock signal with software configurable phase delay
  2. Clock signal with hardware configurable phase delay
  3. Clock return
  4. Clock inversion at MCU