The digital interface with clock edge compensation with software configurable phase delay is shown in Figure 4-8. The timing diagram shows a clock signal with a clock frequency of 20 MHz, representing the clock signal which is fed into the isolated Delta-Sigma modulator, as the first signal. The second signal plotted in the timing diagram represents the data output of the isolated Delta-Sigma modulator for typical specifications given in the data sheet. The third signal represents the 20-MHz clock signal phase-shifted by 10 ns in reference to the first signal which is fed into the clock input of the MCUs SDFM.

Figure 4-8 Timing Diagram C2000 Digital Interface to AMC1305L25 for Typical Specifications in the Data Sheet at 20-MHz Clock Frequency With Clock Edge Compensation With Software Configurable Phase Delay

The calculated setup and hold times including minimum and maximum values are shown in Table 4-4. As the phase delay is configurable in the software, the value of the phase delay can be selected such that the data acquisition timing is centered in the data signal. This allows the maximum possible margin to be available for setup and hold timing so that tolerances in the system do not affect the data acquisition. The calculation tool is providing the margin of the digital timing interface helping to understand the acceptable tolerances of the system. For a selected phase delay of 10 ns, the minimum setup time is 15.6 ns, resulting in a margin of 5.6 ns after subtracting the MCU setup time requirement of 10 ns. The margin for the minimum hold time is calculated accordingly and amounts to 6.7 ns.