Figure 3-1 shows the first compensation method, where an additional phase locked clock signal with a software configurable phase delay is used. For this compensation method the phase-shifted clock signal CLKOUT_delay is used as the clock input to SD0_CLK of the Sigma-Delta Filter Module (SDFM). For other types of Delta-Sigma Modulators and MCUs e.g. C2000 MCUs, the compensation method follows the same principle.

Figure 3-1 AMC1306M25 to AM243x MCU Interface With Software Configurable Clock Phase Delay

The implementation of a second phase-shifted clock signal offers the highest degree of freedom and user configurability. This means that various values for minimum hold time t_h(MIN) of various isolated modulators can be compensated by a simple change to the phase-shift value in software. The clock signals rising edge at the SD0_CLK input is phase-shifted such that the clocking signal complies with the data sampling point of the SDFM, as shown in Figure 3-2. The AM243x PRU_ICSSG PRU Timing Requirements in Sigma Delta Mode are 10 ns for minimum setup time t_{su (SD_D-SD_CLK)} (MIN) = 10 ns and 5 ns for minimum hold time t_{h(SD_CLK-SD_D)} (MIN) = 5 ns. This creates a need for compensation to maintain correct acquisition at the data input SDx_D with reference to the rising clock edge of the SDx_CLK signal as the AMC1306M25 minimum hold time t_h(MIN) is 3.5 ns, but 5 ns can be required. After this compensation method is applied, the 10-ns minimum setup and 5-ns hold timings for the Sigma Delta Mode of the AM243x PRU_ICSSG PRU timing requirements are met, see Figure 3-2.

Figure 3-2 AM243x SDFM Timing With 30-ns Phase-Shifted Clock Signal Input at SD0_CLK (GPIO1_1)