SBAA607A December   2023  – January 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P4 , AM263P4-Q1 , AMC1303M2520 , AMC1305L25 , AMC1306M25 , F29H850TU , F29H859TU-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Challenge With Digital Interface Timing Specifications
  6. 3Design Approach With Clock Edge Delay Compensation
    1. 3.1 Clock Signal Compensation With Software Configurable Phase Delay
    2. 3.2 Clock Signal Compensation With Hardware Configurable Phase Delay
    3. 3.3 Clock Signal Compensation by Clock Return
    4. 3.4 Clock Signal Compensation by Clock Inversion at the MCU
  7. 4Test and Validation
    1. 4.1 Test Equipment and Software
    2. 4.2 Testing of Clock Signal Compensation With Software Configurable Phase Delay
      1. 4.2.1 Test Setup
      2. 4.2.2 Test Measurement Results
    3. 4.3 Testing of Clock Signal Compensation by Clock Inversion at MCU
      1. 4.3.1 Test Setup
      2. 4.3.2 Test Measurement Results
        1. 4.3.2.1 Test Result – No Clock Inversion of Clock Input at GPIO123
        2. 4.3.2.2 Test Result – Clock Inversion of Clock Input at GPIO123
    4. 4.4 Digital Interface Timing Validation by Calculation Tool
      1. 4.4.1 Digital Interface With No Compensation Method
      2. 4.4.2 Commonly Used Method - Reduction of the Clock Frequency
      3. 4.4.3 Clock Edge Compensation With Software Configurable Phase Delay
  8. 5Conclusion
  9. 6References
  10. 7Revision History

4.2.2 Test Measurement Results

The TMS320F28379D was running an internal TI SDFM software project, where the two GPIOs GPIO122 and GPIO123 are configured for SDFM mode. The SDFM data filter is configured for Sinc3 with an oversampling ratio of 64 (OSR64). To conduct the test, a 20-MHz clock signal with a 50% duty cycle is generated with the ePWM4 module and fed into the CLKIN Pin of the AMC1306EVM. The ePWM5 module is configured to output a phase-locked 20-MHz clock signal with 50% duty cycle and 30-ns phase-shift. This signal is fed into SD1_C1 (GPIO123). Note that the AMC1306EVM DOUT data bitstream only changes at the rising clock edge, hence once per clock cycle as described in Section 7.11 Switching Characteristics of the AMC1306 data sheet.

Figure 4-3 shows the oscilloscope measurement and the interface diagram. The clock signal fed into the AMC1306EVM CLKIN Pin is represented by the green waveform on channel 3. The data signal output by the AMC1306EVM is the SD1_D1 (GPIO122) signal in red on channel 2. The phase-shifted clock signal fed into SD1_C1 (GPIO123) is the measured waveform in blue on channel 1. As the SDFM module samples the data signal against the rising edge of the phase-shifted clock signal SD1_C1 (GPIO123), the resulting setup time is approximately 18 ns and the resulting hold time is approximately 24 ns. With that the TMS320F28379D setup and hold timing of minimum 10 ns for the SDFM qualified GPIO (3-sample) mode 0 is met. In addition, this design offers an optimum margin to allow tolerances for changes (positive or negative) in the system propagation delay.

GUID-20231128-SS0I-RT4P-VSZN-KBBTZQ88HRDF-low.svg Figure 4-3 Measurement Results of Digital Interface Timing of AMC1306EVM and TMS320F28379D With Clock Signal Compensation by Software Configurable Phase Delay

Figure 4-4 shows the same measurement results for the test performed with the Sitara AM243x Launchpad. In conclusion the clock signal compensation by using an additional clock signal with a software configurable phase delay is an approved method to meet the MCUs setup and hold timing requirements. This method offers the highest degree of freedom, since not only the value of the phase shift is configurable, but this method also works for a wide range of MCUs due to only requiring an additional GPIO pin for the implementation of a phase shifted clock signal.

GUID-20231128-SS0I-VPJ3-8PPQ-F5MMSCGHS1S2-low.svg Figure 4-4 Measurement Results of Digital Interface Timing of AMC1306EVM and AM243x With Clock Signal Compensation by Software Configurable Phase Delay