SLAA834B May   2018  – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133 , MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729 , MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Configuration of MSP430FR4xx and MSP430FR2xx Devices
  4. 3 In-System Programming of Nonvolatile Memory
    1. 3.1 Ferroelectric RAM (FRAM) Overview
    2. 3.2 FRAM Cell
    3. 3.3 Protecting FRAM Using Write Protection Bits in FR4xx Family
    4. 3.4 FRAM Memory Wait States
    5. 3.5 Bootloader (BSL)
    6. 3.6 JTAG and Security
    7. 3.7 Production Programming
  5. 4 Hardware Migration Considerations
  6. 5 Device Calibration Information
  7. 6 Important Device Specifications
  8. 7 Core Architecture Considerations
    1. 7.1 Power Management Module (PMM)
      1. 7.1.1 Core LDO and LPM3.5 LDO
      2. 7.1.2 SVS
      3. 7.1.3 VREF
    2. 7.2 Clock System
      1. 7.2.1 DCO Frequencies
      2. 7.2.2 FLL, REFO, and DCO Tap
      3. 7.2.3 FRAM Access at 16 MHz and 24 MHz and Clocks-on-Demand
    3. 7.3 Operating Modes, Wakeup, and Reset
      1. 7.3.1 LPMx.5
      2. 7.3.2 Reset
    4. 7.4 Determining the Cause of Reset
    5. 7.5 Interrupt Vectors
    6. 7.6 FRAM and the FRAM Controller
    7. 7.7 RAM Controller (RAMCTL)
  9. 8 Peripheral Considerations
    1. 8.1  Overview of the Peripherals on the FR4xx and FR59xx Families
    2. 8.2  Ports
      1. 8.2.1 Digital Input/Output
      2. 8.2.2 Capacitive Touch I/O
    3. 8.3  Communication Modules
    4. 8.4  Timer and IR Modulation Logic
    5. 8.5  Backup Memory
    6. 8.6  RTC Counter
    7. 8.7  LCD
    8. 8.8  Interrupt Compare Controller (ICC)
    9. 8.9  Analog-to-Digital Converters
      1. 8.9.1 ADC12_B to ADC
    10. 8.10 Enhanced Comparator (eCOMP)
    11. 8.11 Operational Amplifiers
    12. 8.12 Smart Analog Combo (SAC)
  10. 9 ROM Libraries
  11. 10Conclusion
  12. 11References
  13. 12Revision History

8.9.1 ADC12_B to ADC

In FR4xx family, The ADC module supports fast 10-bit or 12-bit analog-to-digital conversions. The module implements a 10-bit or 12-bit SAR core together with sample select control and a window comparator.

In FR59xx family, The ADC12_B module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, and up to 32 independent conversion-and-control buffers. The conversion-and-control buffer allows up to 32 independent analog-to-digital converter (ADC) samples to be converted and stored without any CPU intervention.

  • In FR4xx, up to 10 input channels are available externally and 2 channels available internally. The 1.2- V VREF can be output to a device-specific external channel. The on-chip temperature sensor can be internally connected to channel A12. The 1.5-V VREF can be internally connected to channel A13. For detailed connection, see the analog-to-digital converter (ADC) section in the device-specific data sheet.
  • ADC12_B on the FR59xx supports 8 differential and 16 single-ended external inputs. ADC12_B has a dedicated memory control register for each input channel. This allows the user to set unique properties such as voltage reference input and provides a separate memory buffer for each channel of the ADC. For the ADC12_B on the FR59xx, 32 such memory control registers are provided. When a group of channels is sampled, the conversions results are stored sequentially and can be read after all the channels have completed sampling.
  • In both ADC and ADC12_B, 8, 10, 12-bit resolution can be set, In ADC module, ADCRES.ADCCTL2 register is used and the default setting is 10-bit. In ADC12_B module, ADC12RES.ADC12CTL2 register is used and the default setting is 12-bit.
  • In FR4xx family, the DMA is not supported. In FR59xx family, the DMA is supported in the ADC12_B
  • In FR4xx family, an interrupt vector register ADCIV has six interrupt flag sources including three from the window comparator function. As the comparison, all of the ADC12_B interrupts are handled using the ADC12IV.
  • On ADC clock source and sampling rate, MODOSC, ACLK, MCLK and SMCLK can be set as ADC clock. The conversion time can be calculated in (resolution-bit+2) × ADCDIV × 1/fADCCLK. The sampling time can be set by ADCSHTx.ADCCTL0 to 4, 8, 16,…, or 1024 ADC clock cycles. At the same time, the sampling time should be equal or larger than the min sampling time specified in FR4xx device data sheet. This value is related to the equivalent internal and external resistance and capacitance, resolution, and voltage.
  • In the MSP430FR413x and MSP430FR203x devices, the ADC pin selection is set in the SYSCFG2 register. For other FR4xx devices, ADC pin selection is set in the PxSEL0 and PxSEL1 registers.
  • Because there is only one pair of power supply pins (DVCC and DVSS) in FR4xx devices, to achieve good ADC performance, board design should avoid system noise:
    • Place decoupling capacitors as close as possible to the DVCC pin.
    • Select reference voltage carefully.
    • Do not layout high-frequency toggled digital signals close to power line or ADC input signals.
    • Do not toggle I/O pins while ADC is working.
    • Find more design guidance for ADC on www.ti.com.

Some register names have been changed and some functions have been simplified. For more information when porting firmware, see the MSP430FR4xx and MSP430FR2xx family user's guide.