SLAA834B May   2018  – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133 , MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729 , MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Configuration of MSP430FR4xx and MSP430FR2xx Devices
  4. 3 In-System Programming of Nonvolatile Memory
    1. 3.1 Ferroelectric RAM (FRAM) Overview
    2. 3.2 FRAM Cell
    3. 3.3 Protecting FRAM Using Write Protection Bits in FR4xx Family
    4. 3.4 FRAM Memory Wait States
    5. 3.5 Bootloader (BSL)
    6. 3.6 JTAG and Security
    7. 3.7 Production Programming
  5. 4 Hardware Migration Considerations
  6. 5 Device Calibration Information
  7. 6 Important Device Specifications
  8. 7 Core Architecture Considerations
    1. 7.1 Power Management Module (PMM)
      1. 7.1.1 Core LDO and LPM3.5 LDO
      2. 7.1.2 SVS
      3. 7.1.3 VREF
    2. 7.2 Clock System
      1. 7.2.1 DCO Frequencies
      2. 7.2.2 FLL, REFO, and DCO Tap
      3. 7.2.3 FRAM Access at 16 MHz and 24 MHz and Clocks-on-Demand
    3. 7.3 Operating Modes, Wakeup, and Reset
      1. 7.3.1 LPMx.5
      2. 7.3.2 Reset
    4. 7.4 Determining the Cause of Reset
    5. 7.5 Interrupt Vectors
    6. 7.6 FRAM and the FRAM Controller
    7. 7.7 RAM Controller (RAMCTL)
  9. 8 Peripheral Considerations
    1. 8.1  Overview of the Peripherals on the FR4xx and FR59xx Families
    2. 8.2  Ports
      1. 8.2.1 Digital Input/Output
      2. 8.2.2 Capacitive Touch I/O
    3. 8.3  Communication Modules
    4. 8.4  Timer and IR Modulation Logic
    5. 8.5  Backup Memory
    6. 8.6  RTC Counter
    7. 8.7  LCD
    8. 8.8  Interrupt Compare Controller (ICC)
    9. 8.9  Analog-to-Digital Converters
      1. 8.9.1 ADC12_B to ADC
    10. 8.10 Enhanced Comparator (eCOMP)
    11. 8.11 Operational Amplifiers
    12. 8.12 Smart Analog Combo (SAC)
  10. 9 ROM Libraries
  11. 10Conclusion
  12. 11References
  13. 12Revision History

2 Configuration of MSP430FR4xx and MSP430FR2xx Devices

Table 2-1 summarizes the primary differences among the FR4xx devices.

Table 2-1 F4xx Family Device Comparison
Feature or ModuleFR413x, FR203xFR2433, FR263x, FR253xFR231xFR21xx, FR2000FR235x, FR215xFR267x, FR247x
CPU16-MHz MSP43016-MHz MSP43016-MHz MSP43016-MHz MSP43024-MHz MSP43016-MHz MSP430
Program FRAM15.5KB or 8KB15.5KB or 8KB3.75KB or 2KB3.75KB, 2KB, 1KB, or 0.5KB32KB or 16KB64KB or 32KB
Information FRAM512 bytes512 bytesN/AN/A512 bytes512 bytes
SRAM2KB or 1KB4KB, 2KB, or 1KB1KB1KB or 0.5KB4KB or 2KB8KB or 6KB
Maximum GPIOs601916124443
Interrupt pins16 (P1 and P2)16 (P1 and P2)12 (8 pins of P1 and 4 pins of P2)8 (4 pins each of P1 and P2)32 (P1, P2, P3 and P4)All GPIOs
USCI1 eUSCI_A, 1 eUSCI_B2 eUSCI_A, 1 eUSCI_B1 eUSCI_A, 1 eUSCI_B1 eUSCI_A2 eUSCI_A, 2 eUSCI_B2 eUSCI_A, 2 eUSCI_B
ADCADC10 (10 channel)ADC10 (8 channels)ADC10 (8 channels)ADC10 (8 channels)ADC12 (12 channels)ADC12 (12 channels)
ComparatorN/A(1)N/A111 LP eCOMP, 1 HS eCOMP1 LP eCOMP
Analog featuresN/AN/A1 SAC-L1 (OA), 1 TIAN/A4 SAC-L3N/A
Timer2 Timer_A with 3CC(2), RTC counter, WDT2 Timer_A with 3CC,
2 Timer_A with 2CC,
RTC counter, WDT		2 Timer_B with 3CC,
RTC counter, WDT		1 Timer_B with 3CC,
RTC counter, WDT		3 Timer_B with 3CC,
1 Timer_B with 7CC,
RTC counter, WDT		4 Timer_B with 3CC,
1 Timer_B with 7CC,
RTC counter, WDT
Additional featuresTemperature sensor, brownout reset, capacitive touch I/O, LCD in FR4133Temperature sensor, brownout reset, MPY32, CapTIvate™ technology in FR263x and FR253xTemperature sensor, brownout reset, capacitive touch I/OTemperature sensor, brownout reset, capacitive touch I/OShared voltage reference for ADC, DAC, and eCOMP, low-power REFO selectable, temperature sensor, brownout reset, capacitive touch I/OShared voltage reference for ADC, DAC, and eCOMP, low-power REFO selectable, temperature sensor, brownout reset, MPY32, CapTIvate technology in FR267x
BSLUARTI2C, UARTI2C, UARTUARTI2C, UARTI2C, UART
VCC1.8 V to 3.6 V1.8 V to 3.6 V1.8 V to 3.6 V1.8 V to 3.6 V1.8 V to 3.6 V1.8 V to 3.6 V
Active power126 µA/MHz126 µA/MHz126 µA/MHz126 µA/MHz142 µA/MHz135 µA/MHz
Operating temperature–40°C to 85°C–40°C to 85°C–40°C to 85°C–40°C to 85°C–40°C to 105°C–40°C to 105°C
PackageLQFP64, TSSOP56, TSSOP48VQFN24TSSOP20, TSSOP16, QFN16TSSOP16, QFN24LQFP48, QFN40, TSSOP38LQFP48, VQFN40, VQFN32
(1) N/A = not available
(2) CC = capture/compare registers

Table 2-2 summarizes the memory maps of example FR4xx MCUs.

Table 2-2 Comparison of Memory Maps
AccessFR4133FR2633FR2311FR2111FR2355FR2676
Memory (FRAM)R/W

Optional write protect		15KB15KB3.75KB3.75KB32KB64KB
Main: interrupt vectors and signaturesFFFFh to FF80hFFFFh to FF80hFFFFh to FF80hFFFFh to FF80hFFFFh to FF80hFFFFh to FF80h
Main: code memoryFFFFh to C400hFFFFh to C400hFFFFh to F100hFFFFh to F100hFFFFh to 8000h17FFFh to 8000h
Information memory (FRAM)R/W

Optional write protect		512B
19FFh to 1800h		512B
19FFh to 1800h		N/AN/A512B
19FFh to 1800h		512B
19FFh to 1800h
RAMR/W2KB
27FFh to 2000h		4KB
2FFFh to 2000h		1KB
23FFh to 2000h		1KB
23FFh to 2000h		4KB
2FFFh to 2000h		8KB
3FFFh to 2000h
ROM BSLR1KB
13FFh to 1000h		2KB
17FFh to 1000h
1KB
FFFFFh to FFC00h		2KB
17FFh to 1000h
1KB
FFFFFh to FFC00h		1KB
13FFh to 1000h		2KB
17FFh to 1000h		2KB
17FFh to 1000h
1KB
FFFFFh to FFC00h
PeripheralsR/W4KB
0FFFh to 0020h		4KB
0FFFh to 0020h		4KB
0FFFh to 0020h		4KB
0FFFh to 0020h		4KB
0FFFh to 0020h		4KB
0FFFh to 0020h
ROM libraryRN/ACapTIvate libraries and driver libraries,
12KB
6FFFh to 4000h		N/AN/ACapTIvate libraries, FFT and driver libraries,
20KB
FFBFFh to FAC00h		CapTIvate libraries, FFT and driver libraries,
16KB
C3FFFh to C0000h

The registers of the SYS module differ by device. For details, see the MSP430FR4xx and MSP430FR2xx family user's guide.