SLAA834B May   2018  – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133 , MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729 , MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Configuration of MSP430FR4xx and MSP430FR2xx Devices
  4. 3 In-System Programming of Nonvolatile Memory
    1. 3.1 Ferroelectric RAM (FRAM) Overview
    2. 3.2 FRAM Cell
    3. 3.3 Protecting FRAM Using Write Protection Bits in FR4xx Family
    4. 3.4 FRAM Memory Wait States
    5. 3.5 Bootloader (BSL)
    6. 3.6 JTAG and Security
    7. 3.7 Production Programming
  5. 4 Hardware Migration Considerations
  6. 5 Device Calibration Information
  7. 6 Important Device Specifications
  8. 7 Core Architecture Considerations
    1. 7.1 Power Management Module (PMM)
      1. 7.1.1 Core LDO and LPM3.5 LDO
      2. 7.1.2 SVS
      3. 7.1.3 VREF
    2. 7.2 Clock System
      1. 7.2.1 DCO Frequencies
      2. 7.2.2 FLL, REFO, and DCO Tap
      3. 7.2.3 FRAM Access at 16 MHz and 24 MHz and Clocks-on-Demand
    3. 7.3 Operating Modes, Wakeup, and Reset
      1. 7.3.1 LPMx.5
      2. 7.3.2 Reset
    4. 7.4 Determining the Cause of Reset
    5. 7.5 Interrupt Vectors
    6. 7.6 FRAM and the FRAM Controller
    7. 7.7 RAM Controller (RAMCTL)
  9. 8 Peripheral Considerations
    1. 8.1  Overview of the Peripherals on the FR4xx and FR59xx Families
    2. 8.2  Ports
      1. 8.2.1 Digital Input/Output
      2. 8.2.2 Capacitive Touch I/O
    3. 8.3  Communication Modules
    4. 8.4  Timer and IR Modulation Logic
    5. 8.5  Backup Memory
    6. 8.6  RTC Counter
    7. 8.7  LCD
    8. 8.8  Interrupt Compare Controller (ICC)
    9. 8.9  Analog-to-Digital Converters
      1. 8.9.1 ADC12_B to ADC
    10. 8.10 Enhanced Comparator (eCOMP)
    11. 8.11 Operational Amplifiers
    12. 8.12 Smart Analog Combo (SAC)
  10. 9 ROM Libraries
  11. 10Conclusion
  12. 11References
  13. 12Revision History

8.3 Communication Modules

Both FR4xx and FR59xx families have the eUSCI module. Table 8-2 compares the features of the eUSCI on the two families.

Table 8-2 Comparison of eUSCI Modules on FR4xx and FR59xx
Parameter or FeatureeUSCI (FR4xx)eUSCI (FR59xx)
UART
Enhanced baud rate generationYesYes
TXEPT interrupt (similar to USART)YesYes
Start edge interruptYesYes
Selectable glitch filterYesYes
Interrupt vector generatorYesYes
SPI
Enhanced baud rate generationYesYes
Maximum baud rate5 MHz(1)7 MHz(2)
Interrupt vector generatorYesYes
I2C
Preload of transmit bufferYesYes
Clock low timeoutYesYes
Byte counterYesYes
Multiple slave addressingYesYes
Address bit maskYesYes
Hardware clear of interrupt flagsYesYes
Interrupt vector generatorYesYes
(1) Calculated based on SPI timing with another MSP430FR4133 device in slave mode. For the formula to calculate the maximum baud rate, see device-specific data sheet.
(2) Calculated based on SPI timing with another MSP430FR5969 device in slave mode. For the formula to calculate the maximum baud rate, see device-specific data sheet.

The eUSCI_A module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. The eUSCI_B module provides support for SPI (3 or 4 pin) and I2C.

The eUSCI module in most FR4xx devices (except for the FR231x, FR235x, FR215x, FR267x, and FR247x) does not support ACLK for the clock source. If the eUSCI clock source does not support ACLK, the eUSCI cannot work in LPM3 mode. See the clock distribution table in the device-specific data sheet for details. A workaround to allow UART or I2C to work in LPM3 mode is to route the ACLK output to the UCA0CLK or UCB0CLK pin externally. This workaround costs two GPIO pins, and it is available only with packages that include an output for the ACLK signal. The clock distribution in the FR231x, FR235x, FR215x, FR267x, and FR247x devices makes ACLK available for the eUSCI module.

The FR4xx devices have eUSCI_A and eUSCI_B modules. See the device-specific data sheet for the number of instances of each module. Table 8-3 summarizes the pin configurations for the communication interfaces.

In FR231x devices, a pin remapping function is available for eUSCI_B0. The USCIBRMP bit in SYSCFG2 register controls eUSCI_B0 pins remapping from P1.0 to P1.3 to P2.2 to P2.5. Only one port can be selected and valid at one time.

In MSP430 FR21xx and FR2000 devices, the pin remapping functions are available for eUSCI_A and Timer_B. The USCIARMP bit in the SYSCFG3 register controls eUSCI_A pin remapping from P1.4 to P1.7 to P1.0 to P1.3. The TBRMP bit in the SYSCFG3 register controls Timer_B output pin remapping from P1.6 to P1.7 to P2.0 to P2.1. Only one port can be selected and valid at one time.

Table 8-3 FR4xx eUSCI Pin Configurations
eUSCI_A0Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xUARTSPI
P1.0P1.4P1.7P1.7, P1.3P1.7P1.4(1),
P5.
2(2)		TXDSIMO
P1.1P1.5P1.6P1.6, P1.2P1.6P1.5(1),
P5.1(2)		RXDSOMI
P1.2P1.6P1.5P1.5, P1.1P1.5P1.6(1),
P5.0(2)		–SCLK
P1.3P1.7P1.4P1.4, P1.0P1.4P1.7(1),
P4.7(2)		–STE
eUSCI_A1Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xUARTSPI
Not availableP2.6Not availableNot availableP4.3P2.6TXDSIMO
P2.5P4.2P2.5RXDSOMI
P2.4P4.1P2.4–SCLK
P3.1P4.0P3.1–STE
eUSCI_B0Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xI2CSPI
P5.0P1.0P1.0, P2.2Not availableP1.0P1.0(1),
P5.6(2)		–STE
P5.1P1.1P1.1, P2.3P1.1P1.1(1),
P5.5(2)		–SCLK
P5.2P1.2P1.2, P2.4P1.2P1.2(1),
P4.6(2)		SDASIMO
P5.3P1.3P1.3, P2.5P1.3P1.3(1),
P4.5(2)		SCLSOMI
eUSCI_B1Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xI2CSPI
Not availableNot availableNot availableNot availableP4.4P2.7(1),
P5.4(2)		–STE
P4.5P3.5(1),
P5.3(2)		–SCLK
P4.6P3.2(1),
P4.4(2)		SDASIMO
P4.7P3.6(1),
P4.3(2)		SCLSOMI
(1) This is the mappable default function that is controlled by the USCIBRMP or USCIARMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.
(2) This is the mappable function that is controlled by the USCIBRMP or USCIARMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.