SLAA834B May   2018  – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133 , MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729 , MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Configuration of MSP430FR4xx and MSP430FR2xx Devices
  4. 3 In-System Programming of Nonvolatile Memory
    1. 3.1 Ferroelectric RAM (FRAM) Overview
    2. 3.2 FRAM Cell
    3. 3.3 Protecting FRAM Using Write Protection Bits in FR4xx Family
    4. 3.4 FRAM Memory Wait States
    5. 3.5 Bootloader (BSL)
    6. 3.6 JTAG and Security
    7. 3.7 Production Programming
  5. 4 Hardware Migration Considerations
  6. 5 Device Calibration Information
  7. 6 Important Device Specifications
  8. 7 Core Architecture Considerations
    1. 7.1 Power Management Module (PMM)
      1. 7.1.1 Core LDO and LPM3.5 LDO
      2. 7.1.2 SVS
      3. 7.1.3 VREF
    2. 7.2 Clock System
      1. 7.2.1 DCO Frequencies
      2. 7.2.2 FLL, REFO, and DCO Tap
      3. 7.2.3 FRAM Access at 16 MHz and 24 MHz and Clocks-on-Demand
    3. 7.3 Operating Modes, Wakeup, and Reset
      1. 7.3.1 LPMx.5
      2. 7.3.2 Reset
    4. 7.4 Determining the Cause of Reset
    5. 7.5 Interrupt Vectors
    6. 7.6 FRAM and the FRAM Controller
    7. 7.7 RAM Controller (RAMCTL)
  9. 8 Peripheral Considerations
    1. 8.1  Overview of the Peripherals on the FR4xx and FR59xx Families
    2. 8.2  Ports
      1. 8.2.1 Digital Input/Output
      2. 8.2.2 Capacitive Touch I/O
    3. 8.3  Communication Modules
    4. 8.4  Timer and IR Modulation Logic
    5. 8.5  Backup Memory
    6. 8.6  RTC Counter
    7. 8.7  LCD
    8. 8.8  Interrupt Compare Controller (ICC)
    9. 8.9  Analog-to-Digital Converters
      1. 8.9.1 ADC12_B to ADC
    10. 8.10 Enhanced Comparator (eCOMP)
    11. 8.11 Operational Amplifiers
    12. 8.12 Smart Analog Combo (SAC)
  10. 9 ROM Libraries
  11. 10Conclusion
  12. 11References
  13. 12Revision History

7.2.3 FRAM Access at 16 MHz and 24 MHz and Clocks-on-Demand

While most FR4xx devices can source MCLK at a maximum frequency of 16 MHz, the FR235x and FR215x devices can source MCLK at 24 MHz. FRAM access is limited to 8 MHz by the FRAM controller, and wait states are required when MCLK is greater than 8 MHz. For configuring wait states, see Section 3.4. Code execution from RAM and accesses to peripherals can be carried out at 16 MHz.

The clock system on FR4xx and FR59xx devices supports the 'clocks-on-demand' feature. This feature allows the LPM settings to be overridden by a clock request. As long as there is an active request for a clock from a peripheral, the clock remains on, regardless of the LPM setting. It is left to the user to disable any modules that request the clock source and prevent the device from entering the required LPM. As an option, this feature can be disabled using the Clock System Control 8 (CSCTL8) in FR4xx device and Clock System Control 6 (CSCTL6) in FR59xx devices. Hence, FR4xx devices can achieve the same outstanding low-power performance on the clock system.

Table 7-1 lists important differences between the clock systems.

Table 7-1 Comparison of FR4xx and F59xx Clock Systems
Parameter or FeatureFR4xxFR59xx
Maximum system frequency24 MHz16 MHz
XT1 oscillatorSupports LF or LF and HF modes(1)Supports only LF mode
XT2 oscillatorNot availableSupports up to 24 MHz
DCO rangeFactory-provided frequencies only with software trimmingCalibrated frequencies only
FLLAvailableNot available
REFOAvailable/Low power modeNot available
LFMODCLK (MODOSC/128)Not availableAvailable
VLO controlAvailable with VLOAUTOOFF.CSCTL5Available with VLOOFF.CSCTL4
Production calibrated frequenciesNone1 MHz, 2.66 MHz, 3.5 MHz, 4 MHz, 5.3 MHz, 7 MHz, 8 MHz, 16 MHz, 21 MHz, and 24 MHz
Clock sources for MCLKDCOCLKDIV, XT1CLK, REFOCLK, VLOCLKHFXTCLK, LFXTCLK, VLOCLK, LFMODCLK, DCOCLK, MODCLK
Clock sources for SMCLKMCLKHFXTCLK, LFXTCLK, VLOCLK, LFMODCLK, DCOCLK, MODCLK
Clock sources for ACLKXT1CLK, REFOCLK, VLO (supported in the enhanced clock system devices including FR235x, FR215x, FR267x, and FR247x)LFXTCLK, VLOCLK, LFMODCLK (MODOSC/128)
External crystal fail-safe operationsXT1
LF: defaults to REFOCLK,XT1,
HF: defaults to DCOCLKDIV		XT1
LF: defaults to LFMODCLKXT2,
HF: defaults to MODOSC
RegistersCSCTL0 to CSCTL8CSCTL0 to CSCTL6
DCO bits9 Fixed
Internal load capacitors for XT1 oscillatorNot availableNot available
(1) Some FR4xx MCUs support XT1 HF mode. See the device-specific data sheet for details.