SLAAE56A November   2022  – March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM32 MCUs to MSPM0 MCUs
  4. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 CubeIDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 CubeMX vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  5. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
    6. 3.6 Interrupt and Events Comparison
    7. 3.7 Debug and Programming Comparison
  6. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  7. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  8. 6Revision History

3.4 Clocks Summary and Comparison

STM32G and MSPM0 contain internal oscillators which source primary clocks. The clocks can be divided to source other clocks and be distributed across the multitude of peripherals.

Table 3-6 Oscillator Comparisons
STM32G0 Oscillators MSPM0 Oscillators

HSI16RC 16 MHz

SYSOSC(1)

HSI48RC 48 MHz

SYSOSC

LSI RC 32 kHz

LFOSC

HSE OSC 4-48 MHz

HFXT

LSE OSC 32 kHz

LFXT

I2S_CLKIN

HFCLK_IN (Digital Clock)
(1) SYSOSC is programmable to be 32 MHz, 24 MHz, 16 MHz, or 4 MHz.
Table 3-7 Clock Comparison
STM32G Clock MSPM0 Clock

HSISYS

N/A

PLLPCLK

SYSPLLCLK1

PLLQCLK

SYSPLLCLK1

PLLRCLK

SYSPLLCLK0

N/A

SYSPLLCLK2x(1)

SYSCLK

BUSCLK(2)

HCLK

MCLK

HCLK8

CPUCLK

PCLK

BUSCLK

TIMPCLK

BUSCLK

LPTIMx_IN

LFCLK_IN
(1) SYSPLLCLK2x is twice the speed of the output of the PLL module and can be divided down.
(2) BUSCLK depends on the Power Domain. For Power Domain 0, BUSCLK is ULPCLK. For Power Domain 1, BUSCLK is MCLK.
Table 3-8 Peripheral Clock Sources
Peripheral STM32G Clock Source MSPM0 Clock Source

RTC

LSI, LSE, HSE/32

LFCLK (LFOSC, LFXT)

UART

PCLK, LSE, HSI16, SYSCLK

BUSCLK, MFCLK, LFCLK

SPI

NEED TO FIND

BUSCLK, MFCLK, LFCLK

I2C

PCLK, HSI16, SYSCLK

BUSCLK, MFCLK

ADC

HSI16, SYSCLK, PLLPCLK

ULPCLK, HFCLK, SYSOSC

CAN

PCLK, HSE, PLLQCLK

PLLCLK1, HFCLK

TIMERS

PCLK, TIMPCLK, PLLQCLK

BUSCLK, MFCLK, LFCLK

LPTIM 1/2 (TIMG0/1)

PCLK, LSI, LSE, HSI16, LPTIMX_IN

LFCLK, ULPCLK, LFCLK_IN

RNG

HSI48, PLLQCLK, HSI16/8, SYSCLK

MCLK

The TRM for each device family has a clock tree to help visualize the clock system. Sysconfig can assist with the options for clock division and sourcing for peripherals.