SLAAE56A November   2022  – March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM32 MCUs to MSPM0 MCUs
  4. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 CubeIDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 CubeMX vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  5. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
    6. 3.6 Interrupt and Events Comparison
    7. 3.7 Debug and Programming Comparison
  6. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  7. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  8. 6Revision History

3.6 Interrupt and Events Comparison

Interrupts and exceptions

The MSPM0 and STM32G0 both register and map interrupt and exception vectors depending on the device's available peripherals. A summary and comparison of the interrupt vectors for each family of devices is included in #GUID-9176F851-753B-4474-9130-9F77ACAAC881/GUID-4A5E6815-3F23-4A0F-ABF8-A0D6371817C9. A lower value of priority for an interrupt or exception is given higher precedence over interrupts with a higher priority value. For some of these vectors the priority is user-selectable, and for others it is fixed.

In the MSPM0 and STM32G0, exceptions such as NMI, reset, and hard fault handlers are given negative priority values to indicate that they always have the highest precedence over peripheral interrupts. For peripherals with selectable interrupt priorities, up to 4 programmable priority levels are available on both families of devices.

Table 3-10 Interrupt Comparison
NVIC Number STM32G0 MSPM0x
Interrupt/Exception Priority Interrupt/Exception Priority
- Reset Fixed: -3 Reset Fixed: -3
- NMI Handler Fixed: -2 NMI Handler Fixed: -2
- Hard Fault Handler Fixed: -1 Hard Fault Handler Fixed: -1
- SVCall Handler Selectable SVCall Handler Selectable
- PendSV Selectable PendSV Selectable
- SysTick Selectable SysTick Selectable
0 Window Watchdog Interrupt Selectable INT_GROUP0: WWDT0, DEBUGSS, FLASHCTL, WUC FSUBx, and SYSCTL Selectable
1 Power Voltage Detector Interrupt Selectable INT_GROUP1: GPIO0 and COMP0 Selectable
2 RTC and Timestamp Selectable Timer G1 (TIMG1) Selectable
3 Flash Global Interrupt Selectable UART3(1) Selectable
4 RCC Global Interrupt Selectable ADC0 Selectable
5 EXTI0 and EXTI1 interrupt Selectable ADC1(1) Selectable
6 EXTI2 and EXTI3 interrupt Selectable CANFD0(1) Selectable
7 EXTI4-EXTI15 interrupt Selectable DAC0(1) Selectable
8 UCPD1/UCPD2/USB Selectable Reserved Selectable
9 DMA1 Channel 1 Selectable SPI0 Selectable
10 DMA1 Channel 2 and 3 Selectable SPI1(1) Selectable
11 DMA1 Channel 4-6, and DMA2 Channel 1-5 Selectable Reserved Selectable
12 ADC and Comparator Selectable Reserved Selectable
13 Timer 1 (TIM1), Break, Update, Trigger, and Commutation Selectable UART1 Selectable
14 TIM1 Capture Compare Selectable UART2(1) Selectable
15 TIM2 global interrupts Selectable UART0 Selectable
16 TIM3 and TIM4 global interrupts Selectable TIMG0 Selectable
17 TIM6, LPTIM1, and DAC interrupts Selectable TIMG10(1) Selectable
18 TIM6 and LPTIM2 global interrupts Selectable TIMA0(1) Selectable
19 TIM14 global interrupts Selectable TIMA1 Selectable
20 TIM15 global interrupts Selectable TIMA2(2) Selectable
21 TIM16 and FDCAN0 global interrupts Selectable TIMH0(1) Selectable
22 TIM17 and FDCAN1 global interrupts Selectable Reserved Selectable
23 12C1 global interrupts Selectable Reserved Selectable
24 I2C2 and I2C3 global interrupts Selectable I2C0 Selectable
25 SPI1 global interrupts Selectable I2C1 Selectable
26 SPI2 and SPI3 global interrupts Selectable Reserved Selectable
27 USART1 global interrupts Selectable Reserved Selectable
28 USART2 and LPUART2 global interrupts Selectable AES(1) Selectable
29 USART 3-6 and LPUART1 global interrupts Selectable Reserved Selectable
30 CEC global interrupts Selectable RTC(1) Selectable
31 AES and RNG global interrupts Selectable DMA Selectable
(1) Only available in MSPM0G family of devices.
(2) TIMG4 on MSPM0L family of devices

Event Handler and EXTI (Extended Interrupt and Event Controller)

The MSPM0 devices include a dedicated event manager peripheral, which extends the concept of the NVIC to allow digital events from a peripheral to be transferred to the CPU as interrupts, to the DMA as a trigger, or to another peripheral to trigger a hardware action. The event manager can also perform handshaking with the power management and clock unit (PMCU), to make sure that the necessary clock and power domain are present for triggered event actions to take place.

Figure 3-2 Generic Event Route

In the MSPM0 event manager, the peripheral that generates the event is known as a publisher, and the peripheral, DMA, or CPU that acts based on the publisher is known as the subscriber. The potential combinations of available publisher and subscriber are extremely flexible and can be used when migrating software to replace functionality previously handled by interrupt vectors and the CPU, to bypass the CPU entirely. For example, an I2C-to-UART bridge may previously have triggered a UART transmission upon receipt of an I2C STOP, using an ISR to set a flag, or load the UART TX buffer directly. With the MSPM0 Event handler, the I2C transaction complete event could trigger the DMA to load the UART TX buffer directly, and therefore eliminate the need for any action by the CPU.

See the Events section of the MSPM0G technical reference manual or the MSPM0L technical reference manual to get more details on the use of the event handler in MSPM0.

Not to be confused with the MSPM0 event handler, the STM32G0 family of devices implement an extended interrupt and event controller (EXTI), which allows for the system wake from STOP mode through configurable events from IOs or peripherals. The wakeup features of the STM32G0 EXTI can be best replicated in MSPM0 using the IO wakeup features (see the IOMUX section of the MSPM0 technical reference manuals) and GPIO FastWake (see the GPIO section of the MSPM0 technical reference manuals). If the wakeup is for a single action, the Event handler peripheral is capable of requesting necessary PMCU resources for a peripheral operation to occur, and returning to the applicable low power mode after.