SLAAE56A November 2022 – March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346
The MSPM0 and STM32G0 family of MCUs feature SRAM used for storing application data.
Feature | STM32G0 | MSPM0 |
---|---|---|
SRAM memory |
STM32G0B1xx, G0C1xx: 144KB (128KB with SRAM parity enabled) STM32G071xx, G081xx: 36KB (32KB with SRAM parity enabled) STM32G051xx, G061xx: 18KB (16KB with SRAM parity enabled) STM32G031xx, G041xx: 8KB (8KB with SRAM parity enabled) Zero wait states |
MSPM0Gxx: 32KB to 16KB MSPM0Lxx: 4KB to 2KB Zero wait states Select devices include SRAM parity and ECC. See device data sheet for details |
Zero wait states at maximum CPU clock frequency | Yes |
Yes |
Access resolution | Byte, half-word (16-bits) or full word (32-bits) |
Byte, half-word (16-bits) or full word (32-bits) |
Parity check | Yes |
Yes |
MSPM0 MCUs include low-power high-performance SRAM with zero wait state access across the supported CPU frequency range of the device. SRAM can be used for storing volatile information such as the call stack, heap, and global data, in addition to code. The SRAM content is fully retained in run, sleep, stop, and standby operating modes, but is lost in shutdown mode. A write protection mechanism is provided to allow the application to dynamically write protect the lower 32KB of SRAM with 1KB resolution. On devices with less than 32KB of SRAM, write protection is provided for the entire SRAM. Write protection is useful when placing executable code into SRAM as it provides a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption.