SLAAE72 December   2022 MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
  4. 2Low-Power Features in PMCU
    1. 2.1 Overview
      1. 2.1.1 Power Domains and Power Modes
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Supply Supervisors
      2. 2.2.2 Peripheral Power Control
      3. 2.2.3 VBOOST for Analog Muxes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
      2. 2.3.2 Clocks
      3. 2.3.3 Asynchronous Fast Clock Requests
      4. 2.3.4 Shutdown Mode Handling
  5. 3Low-Power Optimization
    1. 3.1 Low-Power Basics
    2. 3.2 MSPM0 Low-Power Feature Use
      1. 3.2.1 Low-Power Modes
      2. 3.2.2 System Clock and Peripheral Operation Frequency
      3. 3.2.3 I/O Configuration
      4. 3.2.4 Event Manager
      5. 3.2.5 Analog Peripheral Low-Power Features
      6. 3.2.6 Run Code From RAM
    3. 3.3 Software Coding Strategies
    4. 3.4 Hardware Design Strategies
  6. 4Power Consumption Measurement and Evaluation
    1. 4.1 Current Evaluation
    2. 4.2 Current Measurement
      1. 4.2.1 Current Measurement

2.2.2 Peripheral Power Control

PD0 and PD1 power supply is automatically controlled by SYSCTL according to the power mode setting. Users do not need to control the power supply manually.

When PD1 peripherals are forced to a disabled state by SYSCTL upon entry into a STOP or STANDBY mode, most PD1 peripheral configuration settings are retained. See the peripheral-specific chapter in the TRM for details on which peripheral registers are retained.

If a PD1 peripheral was multiplexed to an IO pin (through the IOMUX) in an output configuration, the last valid IO output state is latched upon entry to STOP or STANDBY mode. This feature can be a leakage current source.