SLAAE75A November   2022  – March 2023 MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1 MSPM0L Hardware Design Check List
  4. 2 Power Supplies in MSPM0L Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  5. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  6. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Clock Output (CLK_OUT)
    3. 4.3 Frequency Clock Counter (FCC)
  7. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  8. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
  9. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 I2C and SPI Design Considerations
  10. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High Speed GPIOs
    4. 8.4 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    5. 8.5 Communicate With 1.8-V Devices Without a Level Shifter
    6. 8.6 Unused Pins Connection
  11. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  12. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  13. 11References
  14. 12Revision History

8.1 GPIO Output Switching Speed and Load Capacitance

When using the GPIO as I/O, design considerations must be made to ensure correct operation. As load capacitance becomes larger, the rise/fall time of the I/O pin increases. This capacitance includes pin parasitic capacitance (Ci = 5pF (Typical)) and the effects of the board traces. I/O characteristics are available in the device data sheet. #GUID-2EC8A4C8-8093-41AC-A223-02374C33D562/GUID-2DB7FB01-4546-4826-AC28-667DFDBA74D7 list the I/O output frequency characteristics of the MSPM0L device.

Table 8-1 MSPM0L GPIO Switching Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz
VDD ≥ 2.7 V, CL = 20 pF 32
HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16
VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24
VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32
VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40
ODIO VDD ≥ 1.71 V, FM+, CL= 20 pF to 100 pF 1
tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3 × fmax s
tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL= 20 pF to 100 pF 20 × VDD / 5.5 120 ns
Note:
  • The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
  • The output rise time of open-drain I/Os is determined by the pullup resistance and load capacitance.