SLAAE82 March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346
Description
This example demonstrates how to interface with signals up to 5 V using open-drain IOs (ODIOs) on an MSPM0 device. With the use of external pullup resistors, the open-drain IOs allow for communication across multiple voltage domains at voltage levels higher than the MSPM0 VDD supply voltage.
Figure 1-1 displays a functional block diagram of the peripherals used in this example.
Required Peripherals
This application can use up to two open-drain IOs.
Sub-block Functionality | Peripheral Use | Notes |
---|---|---|
IO | 2 GPIO pins | PA0 and PA1, can only use 5-V tolerant open-drain IOs |
Compatible devices
Based on the requirements in Table 1-1, this example is compatible with the devices in Table 1-2. The corresponding EVM can be used for prototyping.
Compatible Devices | EVM |
---|---|
MSPM0Lxxx | LP-MSPM0L1306 |
MSPM0Gxxx | LP-MSPM0G3507 |
Design steps
Design considerations
Additional Resources