The minimum requirements (power,
reset, and Vcore) with suggested values for MSPM0 hardware setup are shown in Figure 4-3.
- Power pin: TI recommends adding
10uF and 0.1uF capacitors, which are used to remove AC noise on the power
rail.
- Reset pin: TI recommends adding a
47kR pullup resistor and a 10nF pulldown resistor. This makes sure that the
MSPM0 releases from reset, after the power rail is stabilized. For some MSPM0
devices, the reset pin can be reused with another function, like I2C or UART. TI
recommends reducing the resistor and capacitor, such as using a 2.2kR pullup
resistor and 10pF pulldown capacitor.
- Vcore pin: This pin is used to
stabilize the CPU voltage. For some MSPM0 devices, this pin is not included. If
the pin is included, connect the pin to a 0.47uF capacitor.
Other considerations when drawing a
schematic file are listed in Figure 4-4.
- ROSC Pin: If users want to reach
accurate high frequency clock with internal SYSOSC, then 0.1% resistor is
suggested. Some low-cost devices cannot have this function.
- VREF+/VREF- Pin:
- If using an internal
reference,then the G series require a 1uF capacitor between VREF+ and
VREF- to support 4Msps ADC. For L or C series, the capacitor is not
required, as the ADC speed is only support 200Ksps with internal
Vref.
- If using an external
reference, then all the MSPM0 devices require a 1uF capacitor between
VREF+ and VREF-.
- Open-Drain IO: Open-Drain IO
cannot output high voltage from the MCU side, so external pullup resistors are
required, such as a 4.7kR capacitor.
- NRST: If reusing the reset pin as
GPIO, then the pullup resistor and the pulldown capacitor are still required.
This makes sure that the MCU is released from reset state after the power is
stable.
- PA18: PA18 is the invoke pin to
enter bootloader. Make sure this pin is not float or pullup. Otherwise, a user
can change and disable the invoke pin in sysconfig, as shown in Section 7.3.
For further information about
schematics or PCB design references, see the following links.