SLAU847D October 2022 – May 2024 MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1
The SYSOSC can shift from base frequency (32MHz) to low frequency (4MHz), or low frequency back to base frequency, in a single SYSOSC clock cycle with the frequency change being phase aligned to minimize jitter. This feature is particularly well suited for low power, low cost microcontroller applications because it allows a single oscillator to be used to generate two frequencies:
When a high-speed clock is needed (for example, in RUN and SLEEP modes), SYSOSC can run at its base frequency to provide high performance. In such a case, SYSOSC can be used directly to source MCLK so that MCLK can be used by the CPU, DMA, and peripherals clocked by the bus. For peripherals that run continuously but do not require the high clock frequency, the middle frequency system clock (MFCLK) is provided at 4MHz by taking the 32MHz SYSOSC and dividing down by 8.
When the fast 32MHz clock is not needed (for example, if the CPU has completed processing data), then in STOP mode SYSOSC can be gear shifted down to 4MHz in one cycle, and MFCLK switches to being clocked directly by SYSOSC- keeping a continuously running 4MHz clock, but with a reduction in SYSOSC current and no need for a separate oscillator to provide the 4MHz clock. When the CPU is again needed, SYSOSC can be switched back from 4MHz to 32MHz. This transition also occurs in one SYSOSC clock cycle. During the gear shift up, MFCLK switches back to SYSOSC/8 to keep the 4MHz constant frequency. The timing transition between base frequency (32MHz) and low frequency (4MHz) during a gearshift down request is shown in Figure 2-6.
The SYSOSC gearshift mode is tightly integrated with the power management scheme and is controlled by SYSCTL. Gearshift mode can be used when switching between RUN mode and STOP mode (gear down) and STOP mode and RUN mode (gear up). To use gearshift in STOP mode to reduce SYSOSC current, set the USE4MHZSTOP bit in the SYSOSCCFG register. Note that if SYSOSC is configured for 4MHz operation in RUN and SLEEP mode as well as STOP mode (no gear shift), then the USE4MHZSTOP bit does not need to be set to keep the SYSOSC at 4MHz when entering STOP mode.