SLLSF80B October 2019 – March 2022 TCAN1144-Q1 , TCAN1145-Q1 , TCAN1146-Q1
PRODUCTION DATA
The TCAN114x-Q1 has a comprehensive register set with 7-bit addressing.
Table 10-19 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 10-19 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0h + formula | DEVICE_ID_y | Device Part Number | Section 10.6.1 |
8h | REV_ID_MAJOR | Major Revision | Section 10.6.2 |
9h | REV_ID_MINOR | Minor Revision | Section 10.6.3 |
Ah + formula | SPI_RSVD_x | SPI reserved registers | Section 10.6.4 |
Fh | Scratch_Pad_SPI | Read and Write Test Register SPI | Section 10.6.5 |
10h | MODE_CNTRL | Mode configurations | Section 10.6.6 |
11h | WAKE_PIN_CONFIG | WAKE pin configuration | Section 10.6.7 |
12h | PIN_CONFIG | Pin configuration | Section 10.6.8 |
13h | WD_CONFIG_1(1) | Watchdog configuration 1 | Section 10.6.9 |
14h | WD_CONFIG_2(1) | Watchdog configuration 2 | Section 10.6.10 |
15h | WD_INPUT_TRIG(1) | Watchdog input trigger | Section 10.6.11 |
16h | WD_RST_PULSE(1) | Watchdog output pulse width | Section 10.6.12 |
17h | FSM_CONFIG | Fail safe mode configuration | Section 10.6.13 |
18h | FSM_CNTR | Fail safe mode counter | Section 10.6.14 |
19h | DEVICE_RST | Device reset | Section 10.6.15 |
1Ah | DEVICE_CONFIG1 | Device configuration | Section 10.6.16 |
1Bh | DEVICE_CONFIG2 | Device configuration | Section 10.6.17 |
1Ch | SWE_DIS | Sleep wake error timer disable | Section 10.6.18 |
29h | SDO_CONFIG | Enables SDO to also support the nINT function | Section 10.6.19 |
2Dh | WD_QA_CONFIG | Q and A Watchdog configuration | Section 10.6.20 |
2Eh | WD_QA_ANSWER | Q and A Watchdog answer | Section 10.6.21 |
2Fh | WD_QA_QUESTION | Q and A Watchdog question | Section 10.6.22 |
30h | SW_ID1(2) | Selective wake ID 1 | Section 10.6.23 |
31h | SW_ID2(2) | Selective wake ID 2 | Section 10.6.24 |
32h | SW_ID3(2) | Selective wake ID 3 | Section 10.6.25 |
33h | SW_ID4(2) | Selective wake ID 4 | Section 10.6.26 |
34h | SW_ID_MASK1(2) | Selective wake ID mask 1 | Section 10.6.27 |
35h | SW_ID_MASK2(2) | Selective wake ID mask 2 | Section 10.6.28 |
36h | SW_ID_MASK3(2) | Selective wake ID mask 3 | Section 10.6.29 |
37h | SW_ID_MASK4(2) | Selective wake ID mask 4 | Section 10.6.30 |
38h | SW_ID_MASK_DLC(2) | ID Mask, DLC and Data mask enable | Section 10.6.31 |
39h + formula | DATA_y(2) | CAN data byte 7 through 0 | Section 10.6.32 |
41h + formula | SW_RSVD_y(2) | SW_RSVD0 through SW_RSVD4 | Section 10.6.33 |
44h | SW_CONFIG_1(2) | CAN and CAN FD DR and behavior | Section 10.6.34 |
45h | SW_CONFIG_2(2) | Frame counter | Section 10.6.35 |
46h | SW_CONFIG_3(2) | Frame counter threshold | Section 10.6.36 |
47h | SW_CONFIG_4(2) | Mode configuration | Section 10.6.37 |
48h + formula | SW_CONFIG_RSVD_y(2) | SW_CONFIG_RSVD0 through SW_CONFIG_RSVD4 | Section 10.6.38 |
50h | INT_GLOBAL | Global Interrupts | Section 10.6.39 |
51h | INT_1 | Interrupts | Section 10.6.40 |
52h | INT_2 | Interrupts | Section 10.6.41 |
53h | INT_3 | Interrupts | Section 10.6.42 |
54h | INT_CANBUS(1) | CAN Bus fault interrupts | Section 10.6.43 |
55h | INT_GLOBAL_ENABLE | Interrupt enable for INT_GLOBAL | Section 10.6.44 |
56h | INT_ENABLE_1 | Interrupt enable for INT_1 | Section 10.6.45 |
57h | INT_ENABLE_2 | Interrupt enable for INT_2 | Section 10.6.46 |
58h | INT_ENABLE_3 | Interrupt enable for INT_3 | Section 10.6.47 |
59h | INT_ENABLE_CANBUS(1) | Interrupt enable for INT_CANBUS | Section 10.6.48 |
5Ah + formula | INT_RSVD_y | Interrupt Reserved Register INT_RSVD0 through INT_RSVD5 | Section 10.6.49 |
Complex bit access types are encoded to fit into small table cells. Table 10-20 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RH | H R |
Set or cleared by hardware Read |
Write Type | ||
H | H | Set or cleared by hardware |
W | W | Write |
W1C | 1C W |
1 to clear Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |