While parasitic inductance are often minimized through system design, this effect can never be eliminated. Due to this, many gate drivers are designed to handle the transients and help to avoid damage.

Negative voltage handling refers to a gate driver’s ability to withstand negative voltages that can arise from parasitic inductance in the system. Negative voltage tolerances are typically specified for the input and output pins (and for the HS pin of a half-bridge driver). Data sheets often include negative voltage specifications for both DC voltages and repetitive pulses (typically less than 100 ns). For a robust design, take precautions to limit negative voltages through layout and choose a driver that can support the negative voltages expected in the system. Many TI gate driver data sheets include information on reducing negative voltages through layout.