SLVA833D October   2016  – May 2021 TPS2660 , TPS2662 , TPS2663

 

  1.   Trademarks
  2. 1 Surge Test (IEC 61000-4-5)
  3. 2 EFuse Solution for Surge Protection
  4. 3 EFuse Solution Schematic for Surge Protection
  5. 4 Circuit Performance for Surge Tests
  6. 5 EFT Test (IEC 61000-4-4)
  7. 6 EFuse Solution Schematic for EFT protection
  8. 7 Circuit Performance for EFT Tests
  9. 8 Power-Fail Test (IEC 61000-4-29)
  10. 9 EFuse Solution Schematic for Power-Fail Applications
  11. 10Circuit Performance for Power-Fail Tests
  12. 11EFT, Surge and Power-Fail Test Setup
  13. 12Conclusion
  14. 13References
  15. 14Revision History

8 Power-Fail Test (IEC 61000-4-29)

The PLC system must be immune to voltage dips, short interruptions or voltage variations on the DC power ports. Typically, systems are designed to be immune to 5 ms to 10 ms short power interruptions. Major challenges in designing the protection circuits are reverse current blocking and inrush current control. Again, the discrete protection circuits as shown in Figure 1-2 are traditionally used. The TPS2660 based eFuse solution schematic is shown in Figure 9-1. When power fails, integrated back-to-back FETs and high-speed reverse current blocking circuitry prevents bulk capacitor discharge from the output to the input. If the input supply resumes, TPS2660 starts in the current limit mode to quickly ramp up the system bus voltage to the input voltage level. The circuit also provides inrush current control during startup.