SLVK174 September   2024 TPS7H1121-SP

 

  1.   1
  2.   TPS7H1121-SP Single-Event Effects (SEE)
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
    1. 3.1 Device and Test Board Information Continued
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A Total Ionizing Dose from SEE Experiments
  15.   B References

2 Single-Event Effects (SEE)

The primary concern for the TPS7H1121-SP is the robustness against the destructive single-event effects (DSEE): single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H1121-SP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1,2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is latched) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H1121-SP was tested for SEL at the maximum recommended input voltage (VIN) of 14V. The output of the TPS7H1121-SP was configured to the max (13.3V) and min (0.6V) voltages. The output load was configured depending on the output voltage. During the 13.3V testing a constant resistance value of 6.65Ω was used to create a 2A load on the output. During the 0.6V testing a constant resistance value of 1.685Ω was used to create a 0.35A load, which allowed the device to heat to 125°C. For the 6 devices tested under SEL conditions, the TPS7H1121-SP did not exhibit any SEL with heavy-ions with LETEFF = 75MeV·cm2/mg at flux 5.90 x 104 to 9.99 x 104 ions/cm2 ·s, fluence of ≈107 ions/cm2, and a die temperature of 125°C. To see more details on the SEL testing of the TPS7H1121-SP, please refer to Section 7.1.

The TPS7H1121-SP was evaluated for SEB/SEGR at a maximum input voltage of 14V in the enabled and disabled mode with the output voltage configured to be either 13.3V or 0.6V. For the 0.6V case, the load was set to a CR value of 6Ω for a load of 0.1A to prevent the device from heating ≳25°C. Because the MOSFET has shown to be susceptibility to burnout decrement with temperature [5], the device was evaluated while operating under room temperatures. The device was tested with no external thermal control device. During the SEB/SEGR testing, not a single current event was observed, demonstrating that the TPS7H1121-SP is SEB/SEGR-free up to LETEFF = 75 MeV·cm2/mg at a flux of 5.08 x 104 to 1.07 x 105 ions/cm2·s, fluences of ≈107 ions/cm2, and a die temperature of ≈25°C. To see more details on the SEB/SEGR testing of the TPS7H1121-SP, please refer to Section 7.2.

The TPS7H1121-SP was characterized at VIN of 5 and 12V. For SET testing, VOUT was configured to be 3.3V with a CR value of 3.3Ω for a load of 1A. During SET testing the VOUT, SS_TR, and PWRGD signals were monitored. DuringSET testing, not a single transient was observed, demonstrating that the TPS7H1121-SP is SET/SEFI-free up to LETEFF = 75 MeV·cm2/mg at a flux of 6.34 x 104 to 1.05 x 105 ions/cm2·s, fluences of ≈107 ions/cm2, and a die temperature of ≈25°C. To see more details on the SET testing of the TPS7H1121-SP, please refer to Single-Event Transients (SET).