6 Stacking (paralleling) for higher (or lower) load currents

On one hand, processor cores frequently require higher currents with each successive processor generation. On the other hand, some applications may not use all of the functionality of a given processor or may use a less-capable processor within the same processor family, resulting in lower current requirements. Scaling the power supply’s current capability both up and down requires a stackable (parallelable) solution where it is possible to add or remove additional power-supply phases as the current requirements change.

Fixed-frequency DCS-Control devices support stacking. While the specific implementation details vary slightly between each device family, features include current sharing, phase interleaving and interface simplicity.

Current sharing is accomplished through the COMP pin. Since the COMP pin is essentially the small-signal operating point, sharing this pin’s signal between all stacked devices enables fixed-frequency DCS-Control to typically achieve tighter than 10% current-sharing accuracy.

Phase interleaving is accomplished by a dedicated SYNC_OUT pin, which connects to the MODE/SYNC input pin of the next device in the stack. SYNC_OUT is automatically phase-shifted in order to provide ripple cancellation. Through this simple daisy chaining, all devices in the stack operate at the same frequency and with lower ripple than a single-phase design. You can stack a large number of converters and achieve very good phase balancing without needing to specify the number of devices in the stack.

When interfacing to the stack through I2C, communication only happens to the primary device – not each device in the stack – in order to adjust the output voltage, change the operating mode, or read back fault registers. Interfacing to a single device greatly simplifies the communication overhead and PCB routing by both reducing the number of reads and writes and the number of PCB signals that need routing.