SNLA246C October   2015  – April 2024 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Troubleshooting the Application
    1. 2.1 Read and Check Register Values for Basic Health Check
    2. 2.2 Schematic and Layout Checklist
    3. 2.3 Component Checklist
      1. 2.3.1 Magnetics
      2. 2.3.2 Crystal / Oscillator
    4. 2.4 Peripheral Pin Checks
      1. 2.4.1 Power Supplies
      2. 2.4.2 RBIAS Voltage and Resistance
      3. 2.4.3 Probe the XI Clock
      4. 2.4.4 Probe the RESET_N Signal
      5. 2.4.5 Probe the Strap Pins During Initialization
      6. 2.4.6 Probe the Serial Management Interface Signals (MDC, MDIO)
      7. 2.4.7 Probe the MDI Signals
    5. 2.5 Link Quality Check
    6. 2.6 Built-in Self Test With Various Loopback Modes
    7. 2.7 Debugging MAC Interface
      1. 2.7.1 RGMII Debug
      2. 2.7.2 SGMII Debug
  5. 3Application Specific Debugs
    1. 3.1 Improving Link-up Margins for Short Cables
    2. 3.2 Improving Link Margins across Different Channels
    3. 3.3 Link up in 100Mbps Full Duplex Force Mode
    4. 3.4 Unstable Link Up Debug in 1Gbps communication
    5. 3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    6. 3.6 Compliance Debug
    7. 3.7 EMC Debug
    8. 3.8 Tools and References
      1. 3.8.1 DP83867 Register Access
      2. 3.8.2 Extended Register Access
  6. 4Conclusion
  7. 5References
  8. 6Revision History

6 Revision History

Changes from Revision B (December 2022) to Revision C (April 2024)

  • Updated DP83867 Configurations tableGo
  • Updated the register tableGo
  • Updated the schematic and layout checklist hyperlinkGo
  • Added power up sequence noteGo
  • Added timing diagram on when the strapping event occursGo
  • Added steps for debug of MDIO/MDC linesGo
  • Updated Link Quality testGo
  • Added a section on loopback and diagram on BISTGo
  • Added section for debugging SGMII interfaceGo
  • Added Link up in 100Mbps full duplex Force modeGo
  • Added unstable link up debugGo
  • Added errata debug on old revision silicon of DP83867Go
  • Added compliance debug sectionGo
  • Added EMC debug sessionGo

Changes from Revision A (April 2016) to Revision B (December 2022)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added reference register values for PHY linked in 1000 MbpsGo
  • Deleted list of key configuration and status registersGo
  • Added section for schematic and layout checklistGo
  • Added section for component checklistGo
  • Added section for peripheral pin checksGo
  • Updated loopback and BIST sections with testing procedure and corresponding scriptsGo
  • Added section for debugging MAC interfaceGo
  • Added section for application specific debugsGo
  • Added section for tools and referencesGo

Changes from Revision * (October 2015) to Revision A (April 2016)

  • Added Auto-Negotiation status registers to list of key configuration and status registersGo
  • Changed phrasing of descriptions for two and three supply configurationsGo
  • Changed description of three supply power sequencingGo
  • Changed order of RBIAS measurements in Section 2.4.2 Go
  • Added recommendation to confirm strap values in strap status registersGo
  • Added cable connection diagram for termination cableGo
  • Added section on register access.Go
  • Changed images for USB-2-MDIO GUI and MSP430 LaunchPad in Section 3.8.1 Go
  • Changed format of USB-2-MDIO linkGo
  • Added example script for USB-2-MDIOGo
  • Changed format of script from paragraph to codeGo