SNLA340 October 2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TC814R-Q1 , DP83TC814S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1
Table 2-3 shows the PHY address strap comparison between DP83TC811, DP83TC812, DP83TC814, and DP83TG720.
DP83TC811 can support 16 PHY addresses from 0x00 to 0x0F. DP83TC812, DP83TC814, and DP83TG720 can support 9 PHY addresses: 0x00, 0x04, 0x05, 0x08, 0x0A, 0x0C, 0x0D, 0x0E, 0x0F. By provisioning for a pull up and pull down resistor on pin 14 and 15 of the PHY, all four devices can be supported by simply changing the resistor combination.
PIN NO. | PIN NAME | DP83TC811 | DP83TC812, DP83TC814, DP83TG720 | ||||
---|---|---|---|---|---|---|---|
STRAP MODE Table 2-4 | STRAP | STRAP MODE Table 2-5 | STRAP | ||||
15 | RX_DV/CRS_DV/RX_CTRL (DP83TC81x)RX_CTRL (DP83TG720) | PHYADD[0] | PHYADD[2] | PHYADD[0] | PHYADD[2] | ||
Mode 1 | 0 | 0 | Mode 1 | 0 | 0 | ||
Mode 2 | 0 | 1 | Mode 2 | 0 | 1 | ||
Mode 3 | 1 | 0 | NA | NA | NA | ||
Mode 4 | 1 | 1 | Mode 3 | 1 | 1 | ||
14 | RX_ER (DP83TC81x) STRAP_1 (DP83TG720) |
PHYADD[1] | PHYADD[3] | PHYADD[1] | PHYADD[3] | ||
Mode 1 | 0 | 0 | Mode 1 | 0 | 0 | ||
Mode 2 | 0 | 1 | Mode 2 | 0 | 1 | ||
Mode 3 | 1 | 0 | NA | NA | NA | ||
Mode 4 | 1 | 1 | Mode 3 | 1 | 1 |
Table 2-4 shows strap resistor values for DP83TC811 and Table 2-5 show the recommended strap resistor values for DP83TC812, DP83TC814, and DP83TG720. RH are pull-up resistors and RL are pull down resistors.
MODE | IDEAL RH (kΩ) | IDEAL RL (kΩ) |
---|---|---|
1 | OPEN | OPEN |
2 | 10 | 2.49 |
3 | 5.76 | 2.49 |
4 | 2.49 | OPEN |
MODE | IDEAL RH (kΩ) for VDDIO = 3.3 V |
IDEAL RH (kΩ) for VDDIO = 2.5 V |
IDEAL RH (kΩ) for VDDIO = 1.8V |
---|---|---|---|
1 | OPEN | OPEN | OPEN |
2 | 13 | 12 | 4 |
3 | 4.5 | 2 | 0.8 |