SNVAA89A November   2023  – March 2024 LM75A , LM75B , TMP102 , TMP1075 , TMP110 , TMP112 , TMP112-Q1 , TMP175 , TMP175-Q1 , TMP275 , TMP275-Q1 , TMP75 , TMP75-Q1 , TMP75B , TMP75B-Q1 , TMP75C , TMP75C-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Devices Covered in Application Note: Package Pinout and Spec Compatibility
    1. 2.1 TMP1075: Latest Generation LM75 Sensor in Industry-Standard Packages for Cost-Optimized Designs
    2. 2.2 TMP110: LM75-Based Temp Sensor in Small X2SON Package for the Highest Cost-Efficiency
    3. 2.3 TMP112-Q1: Functional Safety-Capable, LM75-Based Sensor for Automotive Designs
  6. 3 Software Compatibility
  7. 4 TMP1075 Cost-Optimized Dual-Source Layout Using TMP110
  8. 5 Linux Driver
  9. 6 Conversion Time and Resolution Setting Highlights
  10. 7 Interpreting Digital Temperature Output: Data Encoding Compatibility
  11. 8 Summary
  12. 9 References
  13. 10Revision History

3 Software Compatibility

The software specs shown in Table 3-1 were chosen based on the following criteria:

  • TMP275, TMP175, and TMP75 have programmable ADCs. Users can choose a 9-bit resolution mode up to a 12-bit resolution mode.
  • I2C Data Hold Times t(HDDAT) are different between the devices. The t(HDDAT) listed in the table below refers to the minimum spec during Fast Frequency Mode.
  • All 75 devices have temperature and limit registers in the exact same locations with the same format.
  • The main changes in registers are Configuration and ID Registers. The Configuration Register holds either 16 or 8 bits of data. The data stored in the Configuration Register is shown in Table 3-1.
Table 3-1 Software Compatibility Table
Devices \CategoriesResolutiont(HDDAT)-FS MinID Register LocationConfig Register
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
TMP10750.0625°C (12 bits)0 ns0 x FOSR1R0F1F0POLTMSD11111111

TMP1075N

0.0625°C (12 bits)100 ns

n/a

OS

R1

R0

F1

F0

POL

TM

SD

1

0

X

0

0

0

0

0

TMP112

0.0625°C (12 bits)

100 ns

n/a

OS

R1

R0

F1

F0

POL

TM

SD

CR1

CR0

AL

EM

0

0

0

0

TMP102

0.0625°C (12 bits)

100 ns

n/a

OS

R1

R0

F1

F0

POL

TM

SD

CR1

CR0

AL

EM

0

0

0

0

TMP1100.0625°C (12 bits)0 nsn/aOSR1R0F1F0POLTMSDCR1CR0ALEM0000
LM75A0.5°C (9 bits)100 ns0 x 7000F1F0POLTMSDn/an/an/an/an/an/an/an/a
LM75B0.5°C (9 bits)100 nsn/a000F1F0POLTMSDn/an/an/an/an/an/an/an/a
TMP275

Selectable 0.5°C (9 bits) -

0.0625 °C (12 bits)

4 nsn/aOSR1R0F1F0POLTMSDn/an/an/an/an/an/an/an/a
TMP175

Selectable 0.5°C (9 bits) -

0.0625 °C (12 bits)

4 nsn/aOSR1R0F1F0POLTMSDn/an/an/an/an/an/an/an/a
TMP75

Selectable 0.5°C (9 bits) -

0.0625 °C (12 bits)

4 nsn/aOSR1R0F1F0POLTMSDn/an/an/an/an/an/an/an/a
TMP75B0.0625°C (12 bits)0 nsn/aOSCRCRFQFQPOLTMSD*(1)*(1)*(1)*(1)*(1)*(1)*(1)*(1)
TMP75C0.0625°C (12 bits)0 nsn/a

*(1)

*(1)

OSFQFQPOLTMSD*(1)*(1)*(1)*(1)*(1)*(1)*(1)*(1)
TMP112-Q10.0625°C (12 bits)100 nsn/aOSR1R0F1F0POLTMSDCR1CR0ALEM0000
TMP75-Q10.0625°C (12 bits)4 nsn/aOSR1R0F1F0POLTMSDn/an/an/an/an/an/an/an/a
TMP75B-Q10.0625°C (12 bits)0 nsn/aOSCRCRFQFQPOLTMSD*(1)*(1)*(1)*(1)*(1)*(1)*(1)*(1)
TMP75C-Q10.0625°C (12 bits)0 nsn/a

*(1)

*(1)

OSFQFQPOLTMSD*(1)*(1)*(1)*(1)*(1)*(1)*(1)*(1)
TMP175-Q10.0625°C (12 bits)4 nsn/aOSR1R0F1F0POLTMSDn/an/an/an/an/an/an/an/a
(1) The * symbol denotes a reserved configured register.